Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-2, 5, 7, and 9-10 are rejected under 35 U.S.C. 103 as unpatentable over MIURA (US 20060050036 A1) in view of SHIIBAYASHI (US 20220246109 A1).
Regarding claim 1, MIURA (Fig. 5) discloses a gamma voltage generation circuit comprising:
a first voltage divider (Fig. 5 and [0008]; voltage divider 51) configured to output a plurality of voltages having different voltage levels ([0008]; voltage divider 51 generates a plurality of voltage signals V1-Vn) between a high potential reference voltage (high voltage VDD) and a low potential reference voltage (low voltage VSS);
a plurality of amplifiers (Fig. 5 and [0008]-[0009]; amplifiers OP) configured to transmit the voltages (voltage signals V1-Vn) output from the first voltage divider (voltage divider 51) to output terminals of the amplifiers (amplifiers OP) as gamma voltages (Fig. 5 and [0008]-[0009]);
a second voltage divider (Fig. 5 and [0009]; voltage divider 52) connected between the high potential reference voltage (high voltage VDD) and the low potential reference voltage (low voltage VSS) and connected to the output terminals of the amplifiers (amplifiers OP).
MIURA (Fig. 5) does not disclose the one or more self-drivers as claimed. However, MIURA (Fig. 1) discloses one or more self-drivers (Fig. 1 and [0025]-[0026]; output circuit 14) connected to the second voltage divider (voltage divider 16) to adjust at least one of gamma voltages other than the gamma voltages output from the amplifiers (Fig. 1 and [0025], amplifiers 13; Figs. 1-2 and [0030]-[0038], gamma voltage adjustments and generation of voltage signals V1-Vn), wherein the self-drivers include a first transistor and a second transistor connected in series (Fig. 1; output circuit 14 including a transistor MN1 and a transistor MP1 connected in series). The examiner further cites SHIIBAYASHI as a reference. SHIIBAYASHI (Figs. 2-3 and 7) discloses the gamma voltage generation circuit, comprising one or more self-drivers (Figs. 3 and 7 [0056]-[0059]; output circuit SP) connected to the second voltage divider (voltage divider LD) to adjust at least one of gamma voltages other than the gamma voltages output from the amplifiers (Figs. 3 and 7 and [0060], amplifiers GB; Figs. 5-6 and [0065]-[0069] and [0072]-[0078], gamma voltage adjustments and generation of voltage signals V1-Vn), wherein the self-drivers include a first transistor and a second transistor connected in series (Figs. 3 and 7; output circuit SP including a transistor Q1 and a transistor Q2 connected in series). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the output circuit as taught by MIURA (Fig. 1) or the output circuit as taught by SHIIBAYASHI to the gamma voltage generation circuit of MIURA (Fig. 5). The combination/motivation would be to provide a gamma voltage generation circuit that is capable of generating multi-level gamma voltages with an improved stability.
Regarding claim 2, MIURA in view of SHIIBAYASHI discloses the gamma voltage generation circuit according to claim 1, MIURA (Fig. 1) discloses wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor (Fig. 1 and [0026]; transistor MN1 is a n-channel transistor and transistor MP1 is a p-channel transistor). SHIIBAYASHI (Figs. 2-3 and 7) also discloses wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor (Figs. 3 and 7 and [0056]; transistor Q1 is a n-channel transistor and transistor Q2 is a p-channel transistor).
Regarding claim 5, MIURA in view of SHIIBAYASHI discloses the gamma voltage generation circuit according to claim 2, SHIIBAYASHI (Figs. 3 and 7) discloses wherein the first transistor (transistor Q1) includes a gate electrode connected to a voltage division node of the first voltage divider (a voltage division node to output a voltage VGn), a first electrode connected to a driving voltage (driving voltage VDD), and a second electrode connected to an (i+1)th gamma voltage corresponding to a voltage output from the voltage division node (gamma voltage Vn corresponding to voltage VGn from the voltage division node), where i is a natural number, and wherein the second transistor (transistor Q2) includes a gate electrode connected to the voltage division node of the first voltage divider (a voltage division node to output a voltage VGn), a first electrode connected to the (i+1)th gamma voltage (gamma voltage Vn corresponding to voltage VGn from the voltage division node), and a second electrode connected to a ground voltage (ground voltage VSS). MIURA (Fig. 1) discloses the same features as claimed. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the output circuit as taught by MIURA (Fig. 1) or the output circuit as taught by SHIIBAYASHI to the gamma voltage generation circuit of MIURA (Fig. 5) for the same reasons above.
Regarding claim 7, MIURA in view of SHIIBAYASHI discloses the gamma voltage generation circuit according to claim 5, both MIURA and SHIIBAYASHI discloses wherein the (i)th gamma voltage is higher than the (i+1)th gamma voltage, and wherein the (i+2)th gamma voltage is lower than the (i+1)th gamma voltage (MIURA’s Figs. 1 and 5 and SHIIBAYASHI’s Figs. 3 and 7; gamma voltage is generated by voltage divider 16 or LD, therefore, the output gamma voltage V1>V2>V3).
Regarding claim 9, MIURA (Figs. 4-5) discloses a source driver circuit comprising:
a data driver (Fig. 4; data driver 42) configured to convert source data to data voltages based on gamma voltages (gamma voltages from gamma voltage generator 41); and
a gamma voltage generator (Figs. 4-5; gamma voltage generator 41) configured to generate the gamma voltages, wherein the gamma voltage generator (gamma voltages from gamma voltage generator 41) includes:
a first voltage divider (Fig. 5 and [0008]; voltage divider 51) configured to output a plurality of voltages having different voltage levels ([0008]; voltage divider 51 generates a plurality of voltage signals V1-Vn) between a high potential reference voltage (high voltage VDD) and a low potential reference voltage (low voltage VSS);
a plurality of amplifiers (Fig. 5 and [0008]-[0009]; amplifiers OP) configured to transmit the voltages (voltage signals V1-Vn) output from the first voltage divider (voltage divider 51) to output terminals of the amplifiers (amplifiers OP) as gamma voltages (Fig. 5 and [0008]-[0009]);
a second voltage divider (Fig. 5 and [0009]; voltage divider 52) connected between the high potential reference voltage (high voltage VDD) and the low potential reference voltage (low voltage VSS) and connected to the output terminals of the amplifiers (amplifiers OP).
MIURA (Fig. 5) does not disclose the one or more self-drivers as claimed. However, MIURA (Fig. 1) discloses one or more self-drivers (Fig. 1 and [0025]-[0026]; output circuit 14) connected to the second voltage divider (voltage divider 16) to adjust at least one of gamma voltages other than the gamma voltages output from the amplifiers (Fig. 1 and [0025], amplifiers 13; Figs. 1-2 and [0030]-[0038], gamma voltage adjustments and generation of voltage signals V1-Vn), wherein the self-drivers include a first transistor and a second transistor connected in series (Fig. 1; output circuit 14 including a transistor MN1 and a transistor MP1 connected in series). The examiner further cites SHIIBAYASHI as a reference. SHIIBAYASHI (Figs. 2-3 and 7) discloses the gamma voltage generation circuit, comprising one or more self-drivers (Figs. 3 and 7 [0056]-[0059]; output circuit SP) connected to the second voltage divider (voltage divider LD) to adjust at least one of gamma voltages other than the gamma voltages output from the amplifiers (Figs. 3 and 7 and [0060], amplifiers GB; Figs. 5-6 and [0065]-[0069] and [0072]-[0078], gamma voltage adjustments and generation of voltage signals V1-Vn), wherein the self-drivers include a first transistor and a second transistor connected in series (Figs. 3 and 7; output circuit SP including a transistor Q1 and a transistor Q2 connected in series). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the output circuit as taught by MIURA (Fig. 1) or the output circuit as taught by SHIIBAYASHI to the gamma voltage generation circuit of MIURA (Fig. 5). The combination/motivation would be to provide a gamma voltage generation circuit that is capable of generating multi-level gamma voltages with an improved stability.
Regarding claim 10, MIURA in view of SHIIBAYASHI discloses the source driver circuit according to claim 9, MIURA (Fig. 1) discloses wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor (Fig. 1 and [0026]; transistor MN1 is a n-channel transistor and transistor MP1 is a p-channel transistor). SHIIBAYASHI (Figs. 2-3 and 7) also discloses wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor (Figs. 3 and 7 and [0056]; transistor Q1 is a n-channel transistor and transistor Q2 is a p-channel transistor).
5. Claims 6 and 11 are rejected under 35 U.S.C. 103 as unpatentable over MIURA (US 20060050036 A1) in view of SHIIBAYASHI (US 20220246109 A1) and further in view of HWANG (US 20190272798 A1).
Regarding claim 6, MIURA in view of SHIIBAYASHI discloses the gamma voltage generation circuit according to claim 2, wherein the first transistor includes a gate electrode connected to a voltage division node of the first voltage divider (voltage division node to output a voltage VG connected to gate of transistor Q1 or MN1), wherein the second transistor includes a gate electrode connected to the voltage division node of the first voltage divider (voltage division node to output the voltage VG connected to gate of transistor Q1 or MN1), but does not disclose the first transistor includes a first electrode connected to an (i)th gamma voltage and a second electrode connected to an (i+1)th gamma voltage corresponding to a voltage output from the voltage division node, where i is a natural number, and the second transistor includes a first electrode connected to the (i+1)th gamma voltage, and a second electrode connected to an (i+2)th gamma voltage. However, HWANG discloses the gamma voltage generation circuit, wherein the first switch (Fig. 8; switch SW2) includes a first electrode connected to an (i)th gamma voltage (Fig. 8; e.g., gamma voltage V86) and a second electrode connected to an (i+1)th gamma voltage (Fig. 8; e.g., gamma voltage V87), where i is a natural number, and the second transistor switch (Fig. 8; switch SW3) includes a first electrode connected to the (i+1)th gamma voltage (Fig. 8; e.g., gamma voltage V87), and a second electrode connected to an (i+2)th gamma voltage (Fig. 8; e.g., gamma voltage V88). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HWANG to the output circuit as taught by MIURA and SHIIBAYASHI. The combination/motivation would be to provide a gamma voltage generation circuit that is capable of generating multi-level gamma voltages with an improved stability.
Regarding claim 11, MIURA in view of SHIIBAYASHI and further in view of HWANG discloses the gamma voltage generation circuit according to claim 6, wherein the (i)th gamma voltage is higher than the (i+1)th gamma voltage, and wherein the (i+2)th gamma voltage is lower than the (i+1)th gamma voltage (MIURA’s Figs. 1 and 5 and SHIIBAYASHI’s Figs. 3 and 7; gamma voltage is generated by voltage divider 16 or LD, therefore, the output gamma voltage V1>V2>V3).
6. Claim 12 is rejected under 35 U.S.C. 103 as unpatentable over MIURA (US 20060050036 A1) in view of SHIIBAYASHI (US 20220246109 A1) and further in view of AHN (US 20110175942 A1).
Regarding claim 12, MIURA in view of SHIIBAYASHI discloses the gamma voltage generation circuit according to claim 5, but does not disclose the gamma voltage generation circuit further comprising a first switch element and a second switch element as claimed. However, AHN (Fig. 4) discloses an output circuit further comprising: a first switch element (switch SW3) connected to the gate electrode of the first transistor (transistor M1) to selectively disable the first transistor (transistor M1); and a second switch element (switch SW4) connected to the gate electrode of the second transistor (transistor M2) to selectively disable the second transistor (transistor M2). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from AHN to the output circuit as taught by MIURA and SHIIBAYASHI to further control the operation of the push-pull output circuit.
7. Claim 13 is rejected under 35 U.S.C. 103 as unpatentable over MIURA (US 20060050036 A1) in view of SHIIBAYASHI (US 20220246109 A1) and HWANG (US 20190272798 A1) and further in view of AHN (US 20110175942 A1).
Regarding claim 13, MIURA in view of SHIIBAYASHI and further in view of HWANG discloses the gamma voltage generation circuit according to claim 6, but does not disclose the gamma voltage generation circuit further comprising a first switch element and a second switch element as claimed. However, AHN (Fig. 4) discloses an output circuit circuit further comprising: a first switch element (switch SW3) connected to the gate electrode of the first transistor (transistor M1) to selectively disable the first transistor (transistor M1); and a second switch element (switch SW4) connected to the gate electrode of the second transistor (transistor M2) to selectively disable the second transistor (transistor M2). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from AHN to the output circuit as taught by MIURA and SHIIBAYASHI to further control the operation of the push-pull output circuit.
Allowable Subject Matter
8. Claims 3-4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a gamma voltage generation circuit. The closet prior arts, MIURA (US 20060050036 A1), SHIIBAYASHI (US 20220246109 A1), HWANG (US 20190272798 A1), and AHN (US 20110175942 A1), individually or in combination, discloses A gamma voltage generation circuit comprising: a first voltage divider configured to output a plurality of voltages having different voltage levels between a high potential reference voltage and a low potential reference voltage; a plurality of amplifiers configured to transmit the voltages output from the first voltage divider to output terminals of the amplifiers as gamma voltages; a second voltage divider connected between the high potential reference voltage and the low potential reference voltage and connected to the output terminals of the amplifiers; and one or more self-drivers connected to the second voltage divider to adjust at least one of gamma voltages other than the gamma voltages output from the amplifiers, wherein the self-drivers include a first transistor and a second transistor connected in series, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, but fails to teach wherein the first transistor includes a gate electrode connected to an (i)th gamma voltage, a first electrode connected to a driving voltage, and a second electrode connected to an (i+1)th gamma voltage, where i is a natural number, and wherein the second transistor includes a gate electrode connected to an (i+2)th gamma voltage, a first electrode connected to the (i+1)th gamma voltage, and a second electrode connected to a ground voltage.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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