DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-final communication in response to communications up to preliminary amendment filed 7/16/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In claim 1, the connection between the plurality of first voltage sources and plurality of switches of the first power module.
In claim 1, the connection between the plurality of second voltage sources and plurality of switches of the second power module.
Claims 2-10 contain the indefiniteness of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Depesse 9673431.
With respect to claim 1, figure 7 of Despesse discloses a pulse formation device (10) comprising:
at least one first power module (100) [K1, K2, K3, K4 and voltage sources of 120] connected to one end (L1) of a load terminal (L) [K9]; and
at least one second power module (200) [K1’,K2’,K3’,K4’ and voltage sources connected] connected to the other end (L2) of the load terminal (L) and the first power module (100),
wherein the first power module (100) comprises a plurality of first voltage sources (110) [voltage sources in 120]
and a plurality of switches (S1 to S4) [K1, K2, K3, K4] independently turned on or off,
the second power module (200) comprises a plurality of second voltage sources (210) [voltage sources 120’] and a plurality of switches (S5 to S8) [K1’,K2’,K3’,K4’] independently turned on or off, and
a difference between a first output voltage (V1) [120 connection to K9] of the first power module (100) and a second output voltage (V2) [connection to K9] of the second power module (200) is generated as an output voltage (Vo) between both ends of the load terminal (L).
With respect to claim 2, figure 7 of Despesse discloses the pulse formation device (10) according to claim 1, wherein a plurality of first power modules (100) are provided and connected in series. [switches and voltage sources connected below]
With respect to claim 3, figure 7 of Despesse discloses the pulse formation device (10) according to claim 1, wherein a plurality of second power modules (200) are provided and connected in series. [switches and voltage sources connected below]
With respect to claim 4, figure 7 of Despesse the pulse formation device (10) according to claim 1, wherein the first power module (100) comprises two first voltage sources (110) and first to fourth switches (S1 to S4) disposed on four legs (LG1 to LG4) of an H-bridge circuit, respectively.
With respect to claim 5, figure 7 of Despesse the pulse formation device (10) according to claim 1, wherein the second power module (200) comprises two second first-voltage sources (210) and fifth to eighth switches (S5 to S8) disposed on four legs (LG1 to LG4) of an H-bridge circuit, respectively.
With respect to claim 6, figure 7 of Despesse the pulse formation device (10) according to claim 1, wherein each of the switches (S1 to S8) comprises a MOSFET. [NMOS]
With respect to claim 7, figure 7 of Despesse the pulse formation device (10) according to claim 1, wherein the first voltage source (110) and the second voltage source (210) are DC voltage sources and are connected to the load terminal (L) with opposite polarities.
With respect to claim 8, figure 7 of Despesse the pulse formation device (10) according to claim 1, further comprising: a controller controlling on/off of the switches (S1 to S8). [not shown]
With respect to claim 9, figure 7 of Despesse the pulse formation device (10) according to claim 1, wherein each of the first voltage sources (110) and each of the second voltage sources (210) outputs the same magnitude of voltage. [modules 120 are identical]
With respect to claim 10, figure 7 of Despesse a pulse formation method using the pulse formation device (10) according to claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached on 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
6/24/26