DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 19-21, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation.
All subsequent citations to the specification of a foreign patent documents will be to its translation.
In regards to claim 1, Li as supported by its translation teaches a method for adjusting a memory capacity, applied to a basic input output system (BIOS), the method comprising:
obtaining serial presence detect (SPD) data of a plurality of types of memories comprising a target memory (“For example, the memory configuration parameters (SPD) of different memory particles that may be used in advance in the main board BIOS development stage are in the main board BIOS”, page 6, paragraph 6);
building a data structural body corresponding to each memory parameter in an image of the BIOS (“Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2);
storing SPD data of each type of the memories in a corresponding data structural body based on memory parameters of each type of the memories (“storing the memory configuration parameters of the memory particles configured in different memory in the main board BIOS”, page 7, paragraph 5);
storing a data structural body of each type of the memories in a storage address (“it needs to pre-store the different memory identification code in the main board BIOS”, page 5, paragraph 1) corresponding to each type of the memories (“each memory identification code has memory configuration information of the memory particles matched with it”, page 5, paragraph 3);
reading SPD data of the target memory from the image of the BIOS (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4), wherein the SPD data of the target memory is reserved (“For example, the memory configuration parameters (SPD) of different memory particles that may be used in advance in the main board BIOS development stage are in the main board BIOS”, page 6, paragraph 6), and the target memory is a physical memory without an SPD controller (“at the same time, saving at least one SPD EEPROM chip and the corresponding PCB space on the material,”, page 3, paragraph 13); and
adjusting a memory capacity of the target memory based on the SPD data of the target memory (“In this embodiment, the memory configuration information includes … capacity information”, page 6, paragraph 7);
wherein the adjusting the memory capacity of the target memory based on the SPD data of the target memory comprises:
assigning the SPD data of the target memory to the target memory (“in the step S4, the main control chip reads the different memory identification code, then loading the corresponding memory particle memory configuration parameter from the main board BIOS to perform memory training action, namely parameter adaptation.”, page 6, paragraph 5); and
initializing the target memory to adjust the memory capacity of the target memory (“in the step S4, the main control chip reads the different memory identification code, then loading the corresponding memory particle memory configuration parameter from the main board BIOS to perform memory training action, namely parameter adaptation.”, page 6, paragraph 5);
reading SPD data of the uninitialized memories from the image of the BIOS to initialize the uninitialized memories (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4).
Li as supported by its translation fails to teach that after the adjusting the memory capacity of the target memory based on the SPD data of the target memory, the method further comprises:
checking whether there are uninitialized memories among the memories accessing to a server of the BIOS after the target memory has been initialized;
sequentially recognizing, in response to there being uninitialized memories among the memories, the uninitialized memories among the memories; and
sequentially reading SPD data of the uninitialized memories to sequentially initialize the uninitialized memories.
Ma as supported by its translation teaches that after the adjusting the memory capacity of the target memory based on the SPD data of the target memory, the method further comprises:
checking whether there are uninitialized memories among the memories accessing to a server of the BIOS after the target memory has been initialized (“step S304, judging whether the current memory bank is the last memory slot of the memory bank”, page 6, paragraph 3);
sequentially recognizing, in response to there being uninitialized memories among the memories, the uninitialized memories among the memories otherwise, skipping to step S301 to detect and determine the next memory bank of the memory bank slot”, page 6, paragraph 3); and
sequentially reading SPD data of the uninitialized memories to sequentially initialize the uninitialized memories (“step S203, initially configuring memory parameter;”, page 5, paragraph 5)
in order to quickly locate an abnormal memory bank (page 2, paragraph 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation such that after the adjusting the memory capacity of the target memory based on the SPD data of the target memory, the method further comprises:
checking whether there are uninitialized memories among the memories accessing to a server of the BIOS after the target memory has been initialized;
sequentially recognizing, in response to there being uninitialized memories among the memories, the uninitialized memories among the memories; and
sequentially reading SPD data of the uninitialized memories to sequentially initialize the uninitialized memories
in order to quickly locate an abnormal memory bank (id.).
In regards to claim 19, Li as supported by its translation further teaches an electronic device, comprising:
a memory, a processor, and a computer program stored on the memory and being capable of executing on the processor, wherein the computer program, in response to being executed by the processor, implements the method for adjusting the memory capacity according to claim 1 (“The automatic identification memory particle configuration information device of the embodiment of the present invention includes a processor 60, a memory 61, and a computer program stored in the memory 61 and operable on the processor 60. the processor 60 executes the computer program to realize the automatic adaptive memory particle configuration information method in the embodiment of the step, such as shown in FIG. 1 step S1 to S4”, page 7, paragraph 9).
In regards to claim 20, Li as supported by its translation further teaches a computer non-transitory readable storage medium, wherein instructions in the computer non-transitory readable storage medium, in response to being executed by a processor of an electronic device, enable the electronic device to perform the method for adjusting the memory capacity according claim 1 (“The automatic identification memory particle configuration information device of the embodiment of the present invention includes a processor 60, a memory 61, and a computer program stored in the memory 61 and operable on the processor 60. the processor 60 executes the computer program to realize the automatic adaptive memory particle configuration information method in the embodiment of the step, such as shown in FIG. 1 step S1 to S4”, page 7, paragraph 9).
In regards to claim 21, Li as supported by its translation further teaches that the SPD data of the target memory the SPD data refers to memory configuration data of the target memory (“Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2), and the SPD controller refers to a memory configuration controller (“at the same time, saving at least one SPD EEPROM chip and the corresponding PCB space on the material,”, page 3, paragraph 13).
In regards to claim 26, Li as supported by its translation further teaches that the plurality of types of the memories at least comprise memories of different models and capacities from different memory manufacturers (“different types of memory particles with different types and capacities of different memory particle manufactures”, page 6, paragraph 11).
Claims 3, 22, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation, Ryu et al. (KR-101948152-B1) as supported by its translation, and Feng et al. (US 2024/0012572).
In regards to claims 3 and 27, Li as supported by its translation further teaches that the storing the SPD data of each type of the memories in the corresponding data structural body based on the memory parameters of each type of the memories comprises:
obtaining memory capacity parameters of each type of the memories (“Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2); and
storing the SPD data in the corresponding data structural bodies (“For example, the memory configuration parameters (SPD) of different memory particles that may be used in advance in the main board BIOS development stage are in the main board BIOS”, page 6, paragraph 6), respectively, wherein different SPD data corresponds to different data structural bodies (“each memory identification code has memory configuration information of the memory particles matched with it”, page 5, paragraph 3).
Li as supported by its translation in view of Ma as supported by its translation fails to teach that the memory capacity parameters of each type of the memories are set by a user;
replacing original memory capacity parameters in the SPD data of each type of the memories based on the memory capacity parameters, to generate new SPD data of each type of the memories; and
storing the new SPD data in the corresponding data structural bodies.
Ryu as supported by its translation teaches that the memory capacity parameters of each type of the memories are set by a user (“For example, the user may select the type and / or size of the memory module”, page 4, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ryu as supported by its translation such that the memory capacity parameters of each type of the memories are set by a user because the user knows what memory was intended to be used.
Li as supported by its translation in view of Ma as supported by its translation and Ryu as supported by its translation fails to teach replacing original memory capacity parameters in the SPD data of each type of the memories based on the memory capacity parameters, to generate new SPD data of each type of the memories; and
storing the new SPD data in the corresponding data structural bodies.
Feng teaches replacing original memory capacity parameters in the SPD data of each type of the memories based on the memory capacity parameters, to generate new SPD data of each type of the memories (See paragraph 0022); and
storing the new SPD data in the corresponding data structural bodies (“The updated initialization components 116 may be loaded into the second memory 106, as indicated by the arrow 212. The loading of the updated initialization components 116 may involve replacement of a component of the initialization components 112 with a corresponding component of the updated initialization components 116. For instance, the previous memory information set 110 may be replaced by the common memory information set 210.”, paragraph 0029)
“thereby providing greater flexibility in terms of the model of memory that can be installed in a computing device.” (paragraph 0015)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation, Ryu as supported by its translation, and Feng to include replacing original memory capacity parameters in the SPD data of each type of the memories based on the memory capacity parameters, to generate new SPD data of each type of the memories; and
storing the new SPD data in the corresponding data structural bodies
“thereby providing greater flexibility in terms of the model of memory that can be installed in a computing device.” (id.).
In regards to claim 22, Feng further teaches that before the storing the SPD data and the new SPD data in the corresponding data structural bodies, respectively, the method further comprises:
creating a data structural body corresponding to the new SPD data in the storage address corresponding to each type of the memories to store the new SPD data (See paragraph 0033).
Claims 5, 7, 8, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation and Ryu et al. (KR-101948152-B1) as supported by its translation.
In regards to claims 5 and 28, Li as supported by its translation further teaches that the reading the SPD data of the target memory from the image of the BlOS, wherein the SPD data of the target memory is reserved comprises:
obtaining, in response to server startup, a memory capacity parameter for the target memory after the BlOS enters an initialization phase (“As shown in FIG. 2, the PCB board is electrified, each pull-up resistor and pull-down resistor will generate level change, the level change information through the GPIO pin is obtained by the main control chip.”, page 4, paragraph 12; “in step S3, each memory identification code has memory configuration information of the memory particles matched with it, the main board BIOS through identifying memory identification code, can be correspondingly matched with the memory configuration information of the memory particles matched with the memory identification code, so as to perform information and parameter adaptation.”, page 6, paragraph 3; “Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2); and
reading, from the image of the BIOS, the SPD data, matching the memory capacity parameter, of the target memory (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4).
Li as supported by its translation in view of Ma as supported by its translation fails to teach that the memory capacity parameter is set by a user. Ryu as supported by its translation teaches that the memory capacity parameter is set by a user (“For example, the user may select the type and / or size of the memory module”, page 4, paragraph 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation and Ryu as supported by its translation such that the memory capacity parameter is set by a user because the user knows what memory was intended to be used.
In regards to claim 7, Li as supported by its translation further teaches that the reading, from the image of the BIOS, the SPD data, matching the memory capacity parameter, of the target memory comprises:
determining a target storage address corresponding to the target memory based on a memory type of the target memory (“in step S3, each memory identification code has memory configuration information of the memory particles matched with it, the main board BIOS through identifying memory identification code, can be correspondingly matched with the memory configuration information of the memory particles matched with the memory identification code, so as to perform information and parameter adaptation.”, page 6, paragraph 3); and
reading, based on a preset protocol, the SPD data that matches the memory capacity parameter from the target storage address (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4; “Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2).
In regards to claim 8, Li as supported by its translation further teaches that the reading, based on the preset protocol, the SPD data that matches the memory capacity parameter from the target storage address comprises:
obtaining a target data structural body corresponding to the memory capacity parameter (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4); and
reading, based on the preset protocol, the SPD data that matches the memory capacity parameter in the target data structural body from the target storage address (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4; “Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2).
Claims 12-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation and Feng et al. (US 2024/0012572).
In regards to claim 12, Ma as supported by its translation further teaches that after the checking whether there are uninitialized memories among the memories of the server of the BlOS, the method further comprises:
determining whether the server is started up normally after checking that all the memories have been initialized (“if all normal memory initialization, BIOS will perform other operations, operation is ended”, page 6, paragraph 5).
Li as supported by its translation in view of Ma as supported by its translation fails to teach re-initializing the memories in response to the server being not started up normally. Feng teaches re-initializing the memories in response to the server being not started up normally (“In some cases, it may not be possible to operationalize the first RAM 102 using the first memory information set 226. The failure to operationalize may be due to various reasons, such as an error in the first memory information set 226. To ensure operationalization of the first RAM 102 in such cases, the computing device 100 may utilize the previous memory information set 110 or the common memory information set 210.”, paragraph 0038) to ensure operationalization of the memory (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation and Feng to include re-initializing the memories in response to the server being not started up normally to ensure operationalization of the memory (id.).
In regards to claim 13, Feng further teaches that the re-initializing the memories comprises:
obtaining a minimum memory parameter of the memories, wherein the minimum memory parameter is preset (“Instead, the common memory information set 210 may provide a basic level of operationalization of the applicable RAMs. For instance, a voltage rating specified in the common memory information set 210 may be the least among the voltage ratings of the different RAMs, so that no RAM is supplied with an excessive voltage. Further, a latency specified in the common memory information set 210 may be the highest among the latencies of the different RAMs.”, paragraph 0032);
reading target SPD data corresponding to the minimum memory parameter from the image of the BIOS (“Further, at block 330, the common memory information set 210 backed-up in the third memory 236 may be loaded into the second memory 106 by replacing the previous memory information set 110 with the common memory information set 210.”, paragraph 0050); and
assigning the target SPD data to the memories (“Further, at block 330, the common memory information set 210 backed-up in the third memory 236 may be loaded into the second memory 106 by replacing the previous memory information set 110 with the common memory information set 210.”, paragraph 0050) and initializing the memories (“Further, at block 332, it may be determined if the operationalization is successful using the previous memory information set 110, such as within the predetermined duration. If successful, at block 328, the update process is completed.”, paragraph 0050).
In regards to claim 14, Feng further teaches that after the re-initializing the memories (Figure 3(a)’s 320 leads to Figure 3(b)’s 324), the method further comprises:
in response to the server being started up normally (At block 326, it may be determined if the operationalization completes within the predetermined duration. If the operationalization completes within the predetermined duration, at block 328, the update process is completed.”, paragraph 0049), updating SPD data of the memories in the image of the BIOS (“Referring to FIG. 3(b), at block 324, the first memory information set 226 may be replaced with the previous memory information set 110 in the second memory 106.”, paragraph 0048).
Li as supported by its translation teaches sequentially reading SPD data of the memories from the image of the BIOS (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4); and
sequentially initializing the memories based on the SPD data of the memories to adjust memory capacities of the memories (“in the step S4, the main control chip reads the different memory identification code, then loading the corresponding memory particle memory configuration parameter from the main board BIOS to perform memory training action, namely parameter adaptation.”, page 6, paragraph 5).
In regards to claim 16, Feng further teaches that after the determining whether the server is started up normally, the method further comprises:
ending the memory initialization process in response to the server being started up normally (“If the operationalization completes within the predetermined duration, at block 322, it may be determined that the attempt to the operationalize has succeeded and that the update process is completed.”, paragraph 0046).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation, Ryu et al. (KR-101948152-B1) as supported by its translation, and Park et al. (US 2017/0131927).
In regards to claim 23, Ryu as supported by its translation further teaches that the obtaining the memory capacity parameter set by the user for the target memory comprises:
obtaining the memory capacity parameter set by the user for the target memory (“For example, the user may select the type and / or size of the memory module”, page 4, paragraph 7).
Li as supported by its translation in view of Ma as supported by its translation and Ryu as supported by its translation fails to teach that the obtaining the memory capacity parameter set by the user for the target memory comprises:
in response to the BIOS entering the initialization phase, displaying an interface of the BIOS; and
obtaining the memory capacity parameter set by the user for the target memory based on the interface of the BIOS.
Park teaches that the obtaining the memory capacity parameter set by the user for the target memory comprises:
in response to the BIOS entering the initialization phase, displaying an interface of the BIOS (See paragraphs 0078-0080); and
obtaining the memory capacity parameter set by the user for the target memory based on the interface of the BIOS (“After selecting the safe memory option, information, including the sizes of the safe memory region and the normal memory region, i.e. a start address and an end address of each of these regions, and the capacity reduction ratio (1/k), is determined accordingly. The information is stored in the BIOS (Step S29)”, paragraph 0082)
in order to “safely use a memory without the cell hammer phenomenon” (paragraph 0007).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation, Ryu as supported by its translation, and Park such that that the obtaining the memory capacity parameter set by the user for the target memory comprises:
in response to the BIOS entering the initialization phase, displaying an interface of the BIOS; and
obtaining the memory capacity parameter set by the user for the target memory based on the interface of the BIOS
in order to “safely use a memory without the cell hammer phenomenon” (id.).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation, Ryu et al. (KR-101948152-B1) as supported by its translation, and Inukai (JP 2004-287989) as supported by its translation.
In regards to claim 24, Li as supported by its translation in view of Ma as supported by its translation and Ryu as supported by its translation teaches claim 8. Li as supported by its translation in view of Ma as supported by its translation and Ryu as supported by its translation fails to teach that the obtaining the target data structural body corresponding to the memory capacity parameter comprises:
obtaining a corresponding relationship that is pre-recorded between memory capacity parameters and data structural bodies; and
obtaining the target data structural body corresponding to the memory capacity parameter based on the memory capacity parameter and the corresponding relationship.
Inukai as supported by its translation teaches that the obtaining the target data structural body corresponding to the memory capacity parameter comprises:
obtaining a corresponding relationship that is pre-recorded between memory capacity parameters and data structural bodies (“The illustrated refresh interval setting TB 20 has an entry 21 for storing the memory capacity of the RAM module attached to the RAM module extension connector 7 and an entry 22 for storing a required refresh interval associated with the entry 21. The refresh interval setting TB 20 stores ‘15.6 μsec’ in the entry 22 associated with ‘16 MByte’, ‘32 MByte’, and ‘64 MByte’ in the entry 21, and ‘128 MByte’ in the entry 21. ‘7.8 μsec’ is stored in the entry 22 associated with ‘256 MByte’.”, paragraph 0033; “As described above, the printer according to the present embodiment performs necessary refresh at an optimum refresh interval regardless of the state at the time of shipment from the factory (the state where the RAM is not added) or the case where the RAM is added later.”, paragraph 0052); and
obtaining the target data structural body corresponding to the memory capacity parameter based on the memory capacity parameter and the corresponding relationship (“Then, the CPU 3 determines the ‘refresh interval’ required for the additional RAM module 16 based on the measured capacity of the additional RAM module 16 and the data stored in the refresh interval setting TB 20, and is determined by default.”, paragraph 0044)
which “performs necessary refresh at an optimum refresh interval regardless of the state at the time of shipment from the factory (the state where the RAM is not added) or the case where the RAM is added later” (paragraph 0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation, Ryu as supported by its translation, and Inukai as supported by its translation such that the obtaining the target data structural body corresponding to the memory capacity parameter comprises:
obtaining a corresponding relationship that is pre-recorded between memory capacity parameters and data structural bodies; and
obtaining the target data structural body corresponding to the memory capacity parameter based on the memory capacity parameter and the corresponding relationship
which “performs necessary refresh at an optimum refresh interval regardless of the state at the time of shipment from the factory (the state where the RAM is not added) or the case where the RAM is added later” (id.).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116185729 A) as supported by its translation in view of Ma (CN 106055438 A) as supported by its translation, Feng et al. (US 2024/0012572), and Inukai (JP 2004-287989) as supported by its translation.
In regards to claim 25, Li as supported by its translation further teaches that the in response to the server being started up normally, sequentially reading the SPD data of the memories from the image comprises:
in response to the server being started up normally, obtaining memory capacity parameters of each type of the memories reset by a user (“Preferably, the memory configuration information includes manufacturer information of memory particles, type information, capacity information, P-Bank number, voltage, row/column address number, bit width, and various operation time sequence parameters.”, page 3, paragraph 2); and
sequentially reading the SPD data corresponding to the memory capacity parameters from the image (“S4: after the main control chip receives the memory identification code, taking and loading the memory configuration information of the memory particles matched with the memory identification code from the main board BIOS.”, page 6, paragraph 4).
Li as supported by its translation in view of Ma as supported by its translation and Feng fails to teach sequentially reading the SPD data corresponding to the memory capacity parameters based on the memory capacity parameters. Inukai as supported by its translation teaches sequentially reading the SPD data corresponding to the memory capacity parameters based on the memory capacity parameters (“Then, the CPU 3 determines the ‘refresh interval’ required for the additional RAM module 16 based on the measured capacity of the additional RAM module 16 and the data stored in the refresh interval setting TB 20, and is determined by default.”, paragraph 0044) which “performs necessary refresh at an optimum refresh interval regardless of the state at the time of shipment from the factory (the state where the RAM is not added) or the case where the RAM is added later” (paragraph 0052). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Li as supported by its translation with Ma as supported by its translation, Feng, and Inukai as supported by its translation to include sequentially reading the SPD data corresponding to the memory capacity parameters based on the memory capacity parameters which “performs necessary refresh at an optimum refresh interval regardless of the state at the time of shipment from the factory (the state where the RAM is not added) or the case where the RAM is added later” (id.).
Response to Arguments
Applicant’s arguments, see remarks, filed 13 March 2026, with respect to the claim objection have been fully considered and are persuasive. The claim objection has been withdrawn.
Applicant's arguments, see remarks, filed 13 March 2026, with respect to the prior art rejections have been fully considered but they are not persuasive.
Applicant appears to be arguing that the claimed “image of the BIOS” is not taught by Li’s “main board BIOS”. The Examiner disagrees. The Examiner is interpreting the claimed “image of the BIOS” as being any copy of the BIOS, whether that copy is located in main memory, in a SPI flash device, in an SSD, or elsewhere. Li’s teaching of a main board BIOS is therefore an embodiment of the claimed “image of the BIOS”.
In response to Applicant’s arguments regarding “without an SPD controller”, one of ordinary skill in the art would recognize the Li is discussing a memory without any SPD chips or controllers. Li teaches saving the PCB space for an SPD EEPROM, which can only occur because there is no SPD EEPOM. Even if it was only sometimes there, the space could not be saved on the PCB. Li teaches how the parameters normally read from SPD are instead read from the BIOS. This reinforces the idea that Li is discussing a memory without any SPD chips or controllers. The phrase “saving at least one SPD EEPROM chip” is not implying that there are other SPD EEPROM chips in the system. Instead, it is implying that in some systems two or more SPD EEPROM chips could be saved. This would occur in systems with multiple memory channels, for example, where typically each channel would need its own SPD EEPROM chip.
In response to Applicant’s arguments regarding “adjusting a memory capacity” and “initializing the target memory to adjust the memory capacity”, Li teaches that the memory configuration information includes capacity information (page 6, paragraph 7). Li also teaches that the memory configuration parameters are loaded to the main control chip to perform memory training action, namely parameter adaptation (page 6, paragraph 5). The combination of these teachings show that Li teaches initializing the target memory to adjust the memory capacity.
In response to Applicant’s arguments regarding checking whether there are uninitialized memories, Ma’s steps S304 and S301 do this check because if the current memory bank is not the last, and there is a memory bank in the memory bank slot, there is an uninitialized memory because that memory bank has not been initialized yet but there is a memory bank present.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nathan Sadler/Primary Examiner, Art Unit 2139 3 April 2026
Prosecution Insights