DETAILED ACTION
The instant application having Application No. 19/139,143 has a total of 20 claims pending in the application; there are 2 independent claims and 18 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-3, 5-18, and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ni et al. (Publication Number US 2017/0322899 A1) in view of Hellriegel et al. (Publication Number US 2015/0347345 A1).
As per claim 1, Ni et al. discloses “A circuit board of a graphics processing unit (GPUs 240; FIG. 2), wherein a connector set (represented by lines 252 between the PCIe switch 220 and the CPU 210, as well as by lines 256 to the GPUs 240; FIG. 2), a switch chip set (PCIe switch 220; FIG. 2), and a device slot set are deployed on the circuit board (PCIe slot 230; FIG. 2).” Ni et al. discloses “the first connector is configured to be connected to a first central processing unit (any of the PCIe switch 220 to the CPU0; FIG. 2).” Ni et al. discloses “and the device slot set is configured to be connected to the graphics processing unit (see the GPUs 240; FIG. 2).”
While Ni et al. discloses connections between slots and processors [FIG. 2], Ni et al. does not disclose “the connector set comprises a first connector, a second connector, a third connector, and a fourth connector, the switch chip set comprises a first switch chip and a second switch chip, and the device slot set comprises a first slot set and a second slot set, wherein the first slot set comprises (M+P) device slots, and the second slot set comprises N device slots, N is equal to (M+P),” “the first switch chip is connected to the first connector, the third connector, and M device slots in the first slot set via traces of the circuit board respectively, the second switch chip is connected to the fourth connector and the N device slots in the second slot set via the traces of the circuit board respectively, and the second connector is connected to P device slots in the first slot set via the traces of the circuit board,” “the second connector is configured to be connected to the third connector,” “the third connector is configured to be connected to the second connector or the fourth connector,” or “the fourth connector is configured to be connected to the third connector or a second central processing unit.”
Hellriegel et al. discloses “the connector set comprises a first connector (PCIe switch within a PCIe riser to the local PCIe slot 314; FIG. 6), a second connector (in the form of a cross connect 424 on one of the PCIe riser 300 [FIG. 6] or the data cross-connect; FIG. 7), a third connector (in the form of a cross connect 424 on a second PCIe riser 300 [FIG. 6] or the data cross-connect; FIG. 7), and a fourth connector (PCIe switch within a second PCIe riser to the local PCIe slot 314; FIG. 6), the switch chip set comprises a first switch chip and a second switch chip (PCIe switch within the PCIe rise 300; FIG. 6), and the device slot set comprises a first slot set and a second slot set, wherein the first slot set comprises (M+P) device slots, and the second slot set comprises N device slots, N is equal to (M+P) (the idea of a variable number of slots accessible to only a particular switch is disclosed where through a cross-connect, unless another switch or other gated circuitry is implemented (where eight slots are available), only six slots are available [Paragraph 0048]. See also [Paragraph 0042] where a riser 300 can have up to five slot).” Hellriegel et al. discloses “the first switch chip is connected to the first connector, the third connector, and M device slots in the first slot set via traces of the circuit board respectively, the second switch chip is connected to the fourth connector and the N device slots in the second slot set via the traces of the circuit board respectively, and the second connector is connected to P device slots in the first slot set via the traces of the circuit board (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
Hellriegel et al. discloses “the second connector is configured to be connected to the third connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).” Hellriegel et al. discloses “the third connector is configured to be connected to the second connector or the fourth connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches or to the local PCIe slot 314; FIG. 6).” Hellriegel et al. discloses “the fourth connector is configured to be connected to the third connector or a second central processing unit (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches or to the local PCIe slot 314; FIG. 6).”
Ni et al. and Hellriegel et al. are analogous art in that they in the field of PCIe switches.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ni et al. and Hellriegel et al. as allowing adaptor cards to communicate with each other without having to directly involve the processor is advantageous [Paragraph 0022].
As per claim 2, Hellriegel et al. discloses “The circuit board according of claim 1 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line, and face a same direction, and a distance between the second connector and the third connector, and a distance between the third connector and the fourth connector are both a target distance (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
As per claim 3, Hellriegel et al. discloses “The circuit board according of claim 2 (as disclosed by Ni et al. and Hellriegel et al. above), wherein connectors in the connector set are connected with each other via a connector circuit board, wherein a fifth connector and a sixth connector are deployed on a same side of the connector circuit board, the fifth connector and the sixth connector are connected via a trace of the circuit board, the fifth connector and the sixth connector are both board-to-board connectors, and a distance between the fifth connector and the sixth connector is the target distance (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
As per claim 5, Hellriegel et al. discloses “The circuit board according of claim 3 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the connector circuit board is configured to allow plugging and unplugging operations, to connect the third connector to the second connector, or connect the third connector to the fourth connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
As per claim 6, Hellriegel et al. discloses “The circuit board according of claim 2 (as disclosed by Ni et al. and Hellriegel et al. above), wherein connectors in the connector set are connected with each other via a connection cable comprising two connection heads, wherein a first connection head of the connection cable is connected to the third connector, and a second connection head of the connection cable is configured to be connected to the second connector or the fourth connector (see the use of a cable; Paragraph 0049).”
As per claim 7, Ni et al. discloses “The circuit board according of claim 1 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the connection between the second connector and the third connector is configured to form a balanced topology structure or a common topology structure of the graphics processing unit (each PCIe switch 220 can be connected to the GPUs 240 through a dynamic reconfiguration; FIG. 2; Paragraphs 0029-0030).”
As per claim 8, Hellriegel et al. discloses “The circuit board according of claim 7 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the second connector is connected to the third connector (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
Ni et al. discloses “and the first connector and the fourth connector are respectively connected to different central processing units, to form the balanced topology structure (example of different connections from the PCIe switch to either CPU0 or CPU1; FIG. 2).”
As per claim 9, Hellriegel et al. discloses “The circuit board according of claim 7 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the second connector is connected to the third connector (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6), and the first connector and the fourth connector are connected to a same central processing unit, to form the common topology structure (each PCEe riser 3000 connects to a common PCIe root bridge 312; FIG. 6).”
As per claim 10, Hellriegel et al. discloses “The circuit board according of claim 1 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the connection between the third connector and the fourth connector is configured to form a cascade topology structure of the graphics processing unit (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
As per claim 11, Hellriegel et al. discloses “The circuit board according of claim 10 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the third connector is connected to the fourth connector, and the first connector is connected to the first central processing unit, to form the cascade topology structure (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
As per claim 12, Hellriegel et al. discloses “The circuit board according of claim 1 (as disclosed by Ni et al. and Hellriegel et al. above), wherein M is equal to (N-1), and P is equal to 1 (the idea of a variable number of slots accessible to only a particular switch is disclosed where through a cross-connect, unless another switch or other gated circuitry is implemented (where eight slots are available), only six slots are available [Paragraph 0048]. See also [Paragraph 0042] where a riser 300 can have up to five slot).”
As per claim 13, Hellriegel et al. discloses “The circuit board according of claim 12 (as disclosed by Ni et al. and Hellriegel et al. above), wherein N is equal to 5 (a rise 300 can have up to five slots; Paragraph 0042).”
As per claim 14, Ni et al. discloses “A server system, comprising: a central processing unit set (CPUs 210; FIG. 2), a circuit board of a graphics processing unit and a graphics processing unit set (GPUs 240; FIG. 2), wherein the circuit board of the graphics processing unit is connected between the central processing unit set and the graphics processing unit set (FIG. 2).”
Ni et al. discloses “the first connector is configured to be connected to a first central processing unit in the central processing unit set (any of the PCIe switch 220 to the CPU0; FIG. 2).”
Ni et al. discloses “and the device slot set is configured to be connected to a graphics processing unit in the graphics processing unit set (see the GPUs 240; FIG. 2).”
While Ni et al. discloses connections between slots and processors [FIG. 2], Ni et al. does not disclose “a connector set, a switch chip set and a device slot set are deployed on the circuit board of the graphics processing unit, wherein the connector set comprises a first connector, a second connector, a third connector, and a fourth connector, the switch chip set comprises a first switch chip and a second switch chip, and the device slot set comprises a first slot set and a second slot set, wherein the first slot set comprises (M+P) device slots, and the second slot set comprises N device slots, N is equal to (M+P),” “the first switch chip is connected to the first connector, the third connector, and M device slots in the first slot set via traces of circuit board respectively, the second switch chip is connected to the fourth connector and the N device slots in the second slot set via the traces of circuit board respectively, and the second connector is connected to P device slots in the first slot set via the traces of the circuit board,” “the second connector is configured to be connected to the third connector,” “the third connector is configured to be connected to the second connector or the fourth connector,” or “the fourth connector is configured to be connected to the third connector or a second central processing unit in the central processing unit set.” Hellriegel et al. discloses “a connector set, a switch chip set and a device slot set are deployed on the circuit board of the graphics processing unit (PCIe switch within a PCIe riser to the local PCIe slot 314; FIG. 6), wherein the connector set comprises a first connector (PCIe switch within a PCIe riser to the local PCIe slot 314; FIG. 6), a second connector (in the form of a cross connect 424 on one of the PCIe riser 300 [FIG. 6] or the data cross-connect; FIG. 7), a third connector (in the form of a cross connect 424 on a second PCIe riser 300 [FIG. 6] or the data cross-connect; FIG. 7), and a fourth connector (PCIe switch within a second PCIe riser to the local PCIe slot 314; FIG. 6), the switch chip set comprises a first switch chip and a second switch chip (PCIe switch within the PCIe rise 300; FIG. 6), and the device slot set comprises a first slot set and a second slot set, wherein the first slot set comprises (M+P) device slots, and the second slot set comprises N device slots, N is equal to (M+P) (the idea of a variable number of slots accessible to only a particular switch is disclosed where through a cross-connect, unless another switch or other gated circuitry is implemented (where eight slots are available), only six slots are available [Paragraph 0048]. See also [Paragraph 0042] where a riser 300 can have up to five slot).” Hellriegel et al. discloses “the first switch chip is connected to the first connector, the third connector, and M device slots in the first slot set via traces of circuit board respectively, the second switch chip is connected to the fourth connector and the N device slots in the second slot set via the traces of circuit board respectively, and the second connector is connected to P device slots in the first slot set via the traces of the circuit board (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).” Hellriegel et al. discloses “the second connector is configured to be connected to the third connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).” Hellriegel et al. discloses “the third connector is configured to be connected to the second connector or the fourth connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches or to the local PCIe slot 314; FIG. 6).” Hellriegel et al. discloses “the fourth connector is configured to be connected to the third connector or a second central processing unit in the central processing unit set (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches or to the local PCIe slot 314; FIG. 6).”
Ni et al. and Hellriegel et al. are analogous art in that they in the field of PCIe switches.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ni et al. and Hellriegel et al. as allowing adaptor cards to communicate with each other without having to directly involve the processor is advantageous [Paragraph 0022].
As per claim 15, Hellriegel et al. discloses “The server system according of claim 14 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the second connector is connected to the third connector (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
Ni et al. discloses “the first connector is connected to the first central processing unit in the central processing unit set, and the fourth connector is connected to the second central processing unit in the central processing unit set, to form a balanced topology structure of the graphics processing unit set (each PCIe switch 220 can be connected to the GPUs 240 through a dynamic reconfiguration; FIG. 2; Paragraphs 0029-0030).”
As per claim 16, Hellriegel et al. discloses “The server system according of claim 14 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the second connector is connected to the third connector (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
Ni et al. discloses “and the first connector and the fourth connector are both connected to a third central processing unit in the central processing unit set, to form a common topology structure of the graphics processing unit set (each PCIe switch 220 can be connected to the GPUs 240 through a dynamic reconfiguration; FIG. 2; Paragraphs 0029-0030).”
As per claim 17, Hellriegel et al. discloses “The server system according of claim 14 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the third connector is connected to the fourth connector, and the first connector is connected to a fourth central processing unit in the central processing unit set, to form a cascade topology structure of the graphics processing unit set (through a cross-connect 424 where one PCIe switch cascades to another PCIe switch; FIG. 6).”
As per claim 18, Hellriegel et al. discloses “The server system according to The server system according to wherein the server system further comprises a connector circuit board, wherein the second connector, the third connector and the fourth connector are all board- to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line, and face a same direction, and a distance between the second connector and the third connector, and a distance between the third connector and the fourth connector are both a target distance (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).” Hellriegel et al. discloses “and connectors in the connector set are connected with each other via the connector circuit board, wherein a fifth connector and a sixth connector are deployed on a same side of the connector circuit board, the fifth connector and the sixth connector are connected via a trace of the circuit board, the fifth connector and the sixth connector are both board-to-board connectors, and a distance between the fifth connector and the sixth connector is the target distance (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
As per claim 20, Hellriegel et al. discloses “The server system according of claim 18 (as disclosed by Ni et al. and Hellriegel et al. above), wherein the connector circuit board is configured to allow plugging and unplugging operations, to connect the third connector to the second connector, or connect the third connector to the fourth connector (the cross-connect 424 both the PCIe riser 400 that allows for connections between PCIe switches [FIG. 6]. Another example is the data cross-connect 326 that connects a PCIe slot in one riser to a PCIe slot in another rise; FIG. 7).”
Claims 4 and 19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ni et al. (Publication Number US 2017/0322899 A1) and Hellriegel et al. (Publication Number US 2015/0347345 A1) in view of Scanlon (Patent Number US 10,381,758 B1).
As per claims 4 and 19, Ni et al. and Hellriegel et al. disclose “The circuit board according of claim 3 (as disclosed by Ni et al. and Hellriegel et al. above).” However, Ni et al. and Hellriegel et al. do not disclose a sliding switch as disclosed in the limitation “wherein the connector circuit board is configured to slide on the circuit board of the graphics processing unit, to switch between, a connection between the third connector and the second connector, and a connection between the third connector and the fourth connector.”
Scanlon discloses a sliding switch as disclosed in the limitation “wherein the connector circuit board is configured to slide on the circuit board of the graphics processing unit, to switch between, a connection between the third connector and the second connector, and a connection between the third connector and the fourth connector, by means of sliding (see the slider switch 508; Column 9, lines 9-37; FIG. 5A and 5B).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ni et al. and Hellriegel et al. with elements of Scanlon to allow for the ability of manually switching between connections (as sliding switches are known to one of ordinary skill in the art).
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated June 13, 2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach PCIe switches.
U.S. PATENT NUMBERS:2002/0109688 A1 – slots marked with AGP [FIG. 3]
2005/0270298 A1 – [Paragraph 0016; FIG. 1-3]
2009/0276554 A1 – [Paragraphs 0010-0011, 0021, and 0026]
6,505,263 B1 – [FIG. 1]
7,782,325 B2 – [FIG. 8; Claim 21]
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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/H.W.Y/Examiner, Art Unit 2181 January 8, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181