Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Application No. *** filed on ***. Claims *** are presented for examination and are currently pending.
Claim Objections
Claim 1 is objected to because of the following informalities: this claim recites “a masked translation requests”, this is a typo. Claim 1 further recites “the masked translation request”; because of the previously indicated typo, it’s not clear if there is antecedent bases for this term. For prior art rejection the examiner is interpreting a the masked translation request and hence providing antecedent bases for the later term. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: claim 9 recites “a virtual address”, and “the virtual addresses”; again, there appears to be a typo. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: similar to claim 9, claim 17 recites “a virtual address”, and “the virtual addresses”; again, there appears to be a typo. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: “a virtual address”, and “the virtual addresses”; again, there appears to be a typo. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARM ("MMU-401 System Memory Management Unit Technical Reference Manual," March 14, 2013, provided on IDS) in view of Cai (US 20190108134).
Regarding claim 1, ARM teaches a system comprising: a translation lookaside buffer unit (TBU) configured to map an input translation request to a physical address, wherein the input translation request comprises a virtual address [“The TLB and PTW are the major functional blocks of the MMU-401. The TLB caches frequently used address ranges and the PTW performs page table walks.” (ARM_NPL, p. 2-2); “The MMU-401 applies the following logical processing steps to every transaction” including “Performs the main memory PTW automatically on a TLB address miss.” (ARM_NPL, p. 2-2)] and a stream id [“A StreamID is used to map the incoming transaction to a context by using the stream mapping table.” (ARM_NPL, p. 2-7); “Maps an incoming transaction to one of the contexts using an incoming StreamID.” (ARM_NPL, p. 2-2)],
wherein the translation requests comprising a virtual address [“Virtual address that is used for address lookup.” (Debug Read Data Register, ARM_NPL, p. 3-26)] and a stream id [“A StreamID is used to map the incoming transaction to a context by using the stream mapping table.” (ARM_NPL, p. 2-7); “Maps an incoming transaction to one of the contexts using an incoming StreamID.” (ARM_NPL, p. 2-2)] and
wherein the TBU is configured to map stream ids to masked stream ids [“MASK[i]=0b1 ID[i] is ignored. MASK[i]=0b0 ID[i] is relevant to the match.” (ARM_NPL, p. 3-31)] to generate a masked translation requests comprising the virtual address and the masked stream id [“Specifies whether the entry is included in the stream mapping table search” and Stream Match register uses ID and MASK fields (ARM_NPL, p. 3-31)] and to service the input translation request using the masked translation request [“The MMU-401 applies the following logical processing steps to every transaction” including StreamID-based context mapping and TLB/PTW servicing (ARM_NPL, p. 2-2)].
ARM, however, does not explicitly teach wherein the TBU is configured to map stream ids of related input translation requests to masked stream ids.
Cai, in analogous art, teaches wherein the TBU is configured to map stream ids of related input translation requests to masked stream ids [“the virtual huge page number is an identifier of N consecutive virtual pages” (¶ [0011]); “one entry is used to represent a plurality of virtual-to-physical page mappings” (¶ [0014]); “receiving a virtual address, and calculating a virtual huge page number of the virtual address” (¶ [0012]); “calculating a virtual huge page number of the virtual address” (¶ [0012]); and “if both determining results are yes, determining that a physical page number corresponding to the virtual address …” (¶ [0013])].
ARM, on the one hand, teaches a TLB/MMU/SMMU translation system in which incoming translation-related transactions are associated with a StreamID and are processed using stream match registers having ID and MASK fields, thereby teaching masked StreamID matching in a translation path. Cai, on the other hand, teaches that multiple related translation requests, specifically requests directed to consecutive pages within a common huge-page region, may be serviced using a common huge-page grouping representation, including a virtual huge page number. Under the broadest reasonable interpretation, requests to consecutive pages are “related input translation requests,” and the virtual huge page number / common huge-page grouping representation is reasonably analogous to the claimed masked ID because it is a common reduced representation used for a group of related translation requests.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the StreamID-based TLB translation mechanism of ARM_NPL with the huge-page grouping/compression technique of Cai as a matter of applying a known technique to a known device ready for improvement to yield predictable results.
A person of ordinary skill in the art would have found it obvious to apply that known grouping/compression concept to ARM_NPL’s masked StreamID translation structure so that related requests, reasonably including requests directed to consecutive pages, would be serviced through a common reduced/masked representation. This would have predictably improved the translation mechanism in the same way taught by Cai, namely by reducing distinct translation identities and improving TLB efficiency.
Regarding claim 2, ARM/Cai teach the system of claim 1, wherein the TBU comprises reorder buffering circuitry and stream id masking circuitry that are configured to operate at least partially in parallel [AR_NPL: “TLB Hit-Under-Miss (HUM) support. — Up to four parallel page table walks are supported.”, p. 1-4].
Regarding claim 3, ARM/Cai teach the system of claim 2, wherein the reorder buffering circuitry and the stream id masking circuitry are configured to operate concurrently for a same input translation request [ARM: “The MMU-401 applies the following logical processing steps to every transaction: 1. Determines the security state … 2. Maps an incoming transaction to one of the contexts using an incoming StreamID. 3. Caches frequently used address ranges using the TLB.”; “HUM allows responding to the master if there is a TLB hit for a subsequent transaction while the MMU-401 is performing a translation for a previous transaction that had a TLB miss.”, pp. 2-2, 2-9].
Regarding claim 4, ARM/Cai teach the system of claim 3, wherein the system comprises a translation control unit (TCU) configured to obtain stream id masks for related streams and to provide the stream id masks or masked stream ids to the TBU [ARM: “The MMU-401 uses the APB interface as a programming interface, to permit the software to program the registers”; “The Stream Match registers, SMMU_SMRn, match a transaction with a particular context-mapping register group.”; “MASK[i]=0b1 ID[i] is ignored. MASK[i]=0b0 ID[i] is relevant to the match.”, pp. 2-3, 3-30, 3-31].
Regarding claim 5, ARM/Cai teach the system of claim 4, wherein the TCU is configured to provide the stream id masks or masked stream ids to the TBU whenever a change to a page table is detected [Cai: “performing a page table walk to determine a real physical page number corresponding to the virtual address” ; “determining a target entry to be added” ; “adding the target entry as a new independent entry”, ¶0144-0147].
Regarding claim 6, ARM/Cai teach the system of claim 1, wherein the system comprises multiple different processors that provide input translation requests to the TBU, and wherein the related input translation requests originate from a same processor of the multiple different processors [ARM: Figure 1-1 shows two processors labeled “Cortex-A15” and “Cortex-A15”. The accompanying text also states: “The following are example masters for the MMU-401: Graphics Processor Units (GPUs). Video engines. Direct Memory Access (DMA) controllers. Color LCD (CLCD) controllers. Network controllers.” (p. 1-3); “The MMU-401 provides the address translation that a hypervisor needs to virtualize multiple guest operating systems.” and “The MMU-401 controller provides address virtualization to processors and other bus masters in a system.” (p.1-2)].
Regarding claim 7, ARM/Cai teach the system of claim 1, wherein the TBU is configured to selectively mask input translation requests depending on stream ids of the input translation requests [ARM: “Mask. This bit field specifies whether the StreamID is ignored. The possible values of this bit field are: MASK[i]=0b1 ID[i] is ignored. MASK[i]=0b0 ID[i] is relevant to the match.”, p. 3-31].
Regarding claim 8, ARM/Cai teach the system of claim 1, wherein multiple different input translation requests are mapped to a same masked translation request [Cai: “one combination entry is used to represent a plurality of virtual-to-physical page mappings” and “one entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses.” ¶0011-14, ¶0039-41, and ¶0115-124].
Regarding claims 9-16, these claim(s) limitations are significantly similar to those of claim(s) 1-8; and, thus, are rejected on the same grounds.
Regarding claims 17-19, these claim(s) limitations are significantly similar to those of claim(s) 1-3; and, thus, are rejected on the same grounds.
Regarding claim 20, these claim(s) limitations are significantly similar to those of claim(s) 1; and, thus, are rejected on the same grounds.
Conclusion
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/Ramon A. Mercado/Supervisory Patent Examiner, Art Unit 3658
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