DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishibashi (USPN 6,714,083).
With respect to claim 21, a method (method of operating Fig. 2, further details in Fig. 3) of determining whether a first clock signal and a second clock signal are in phase (determining lock of phase between f1 and f2, see Fig. 3);
the method comprising:
detecting a change of state of a first one of the first and second clock signals at a first time (1 detects when one of f1 and f2 changes from a low state to a high state and generates a high pulse of one of Pu and Pd responsive to the low to high change in state, see Fig. 3),
detecting a change of state of a second one of the first and second clock signals at a second time (1 detects when the other one of f1 and f2 changes from a low state to a high state and generates a high pulse of one of Pu and Pd responsive to the low to high change in state, see Fig. 3 at the end of N-cycle), in response to detecting the change of state of the second one of the first and second clock signals at the second time, comparing the state of the first and second clock signals at the second time (6 compares Pu to Pd and generates a low responsive to both being high); and
determining that the first and second clock signals are in phase based on the first and second clock signals being in the same state at the second time (the circuit 20 lest 6 of Fig. 2 determines that the first and second clock signals are locked in the same state at the second time, see SL high when Pc is pulsed low at N-cycle).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 8-11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (USPN 6,714,083) in view of Lesso (USPN 6,856,202)
With respect to claim 1, Ishibashi discloses, in Figs. 2 and 3, a system (Fig. 2 details of operation disclosed in Fig. 3) for determining whether a first clock signal (f1) and a second clock signal (f2) are in phase (according to the lock detection); the system comprising:
a phase comparator arranged to receive the first clock signal and the second clock signal (1 receiving f1 and f2);
a first detector (6); and
a second detector (20 lest 6), arranged to receive the first clock signal (at 23) and the second clock signal (at 21);
wherein the phase comparator is arranged to generate a first pulse when the first clock signal transitions from a first state to a second state (when f1 transitions from a low to a high, 1 generates Pu at a high level, see Fig. 3);
wherein the phase comparator is arranged to generate a second pulse when the second clock signal transitions from a first state to a second state (when f2 transitions from a low to a high, 1 generates Pd at a high level, see Fig. 3) ;
wherein the first detector is configured to output a first detector output signal when the first and second pulses are generated (6 generates Pc as a low pulse signal when both Pu and Pd are pulsed high, see Fig. 3) ; and
wherein the second detector is arranged to generate a second detector output signal (SL) upon receiving the first detector output signal (upon receiving the total pulse signal of Pc, i.e., the transition from a low back to a high, before the delay time of 7 and Pa falling low SL is generated as a high, see Pc, Pa and SL when SL is pulsed high), the second detector output signal being indicative of whether both the first clock signal and the second clock signal are in the second state (the second detector indicates that f1 and f2 are locked and pulse high at the same time, see Fig. 3).
Ishibashi fails to disclose the construction of the phase detector (1). Thus, Ishibashi fails explicitly to disclose:
“a first latch, arranged to receive the first clock signal;
a second latch, arranged to receive the second clock signal;”
“wherein the first latch is arranged to latch when the first clock signal transitions from a first state to a second state;” and
“wherein the second latch is arranged to latch when the second clock signal transitions from a first state to a second state”.
However, Lesso discloses, in Fig. 2a, a specific phase comparator (2a) comprising:
a first latch (L1), arranged to receive the first clock signal (REFERENCE CLOCK);
a second latch (L2), arranged to receive the second clock signal (DERIVED CLOCK);
wherein the first latch is arranged to latch when the first clock signal transitions from a first state to a second state (latch REFERENCE clock as the high pulse signal of UP when REFERENCE CLOCK transitions from low to high); and
wherein the second latch is arranged to latch when the second clock signal transitions from a first state to a second state (latch DERIVED CLOCK as the high pulse signal of DOWN when DERIVED CLOCK transitions from low to high).
The phase comparator of Lesso is a specific and simply constructed phase comparator capable of generating the output signals as required by the phase comparator of Ishibashi.
It would have been obvious to replace the generic phase comparator 1 of Ishibashi with the specific phase comparator of Fig. 2a of Lesso for the purpose of having a specific phase comparator that is simply constructed.
It is noted that as combined above the first detector will output the first detector output signal when the first and second latches are latched, since the first and second latches of Lesso generate the up and down signals (Pu; Pd) of Ishibashi.
With respect to claim 4, the system of claim 1,wherein the first latch comprises a first resettable D flip flop (L1 of Lesso is resettable), wherein the second latch comprises a second resettable D flip flop (L2 is resettable), and wherein the first resettable D flip flop and the second resettable D flip flop each comprise a respective clocking input and a reset input (each CK and each RB).
With respect to claim 5, the system of claim 4, wherein the first clock signal is provided to the clocking input to the first resettable D flip flop (f1/REFERENCE CLOCK to L1 of Lesso), and wherein the second clock signal is provided to the clocking input to the second resettable D flip flop (f2/DERIVED CLOCK to L2 of Lesso).
7. (Currently Amended) The system of any preceding claim 1,wherein the first latch is configured to detect the change of state of the first clock signal based on the first clock signal transitioning from the first state to the second state and wherein the second latch is configured to detect the change of state of the second clock signal based on the second clock signal transitioning from the first state to the second state.
With respect to claim 8, the system claim 1,wherein the first clock signal and the second clock signal are square waves (f1 and f2 are square waves).
With respect to claim 9, (Currently Amended) The system of any preceding claim 1,wherein the first detector is a first logic gate (the first detector is a logic gate), wherein optionally the logic gate is a first AND gate (the recitation of an “AND” gate is not required since it is claimed to be optional).
With respect to claim 10, the system of any preceding claim 1,wherein the second detector is arranged to receive the first clock signal and the second clock signal, and to determine whether the first clock signal and the second clock signal are in the same state (the second detector is a lock detector and thus determines when f1 and f2 are locked in phase, i.e., rise at the same time).
With respect to claim 11, the system of claim 1,wherein the second detector comprises a second logic gate (e.g., 22) and a third latch (any one of 23 with 24, 21 and 8).
With respect to claim 17, a phase locked loop comprising the system of claim 1 (Fig. 1 of Ishibashi is a phase locked loop).
Allowable Subject Matter
Claims 2-3, 6, 12-16, 18-19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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