DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190303329) in view of Chen et al (US 20230075055).
As to claim 1, Lee discloses a dual basic input/output system (BIOS) system (fig. 3), comprising:
a first BIOS chip (memory 341), configured to run a first BIOS sub-system (par. 20 “store a basic input output system”);
a second BIOS chip(memory 342), configured to run a second BIOS sub-system (par. 20);
a BMC control chip (controller 320), configured to control the second BIOS chip (par. 31), the BMC control chip being connected to the second BIOS chip (via path 332); and
a platform controller hub (PCH 210), configured to control the first BIOS chip (par. 23 “boots device 100 based on the BIOS in memory 141”) and the BMC control chip (“communicate with auxiliary controller 120”), the platform controller hub being connected to the first BIOS chip via a first bus (fig. 1, bus 160) and connected to the BMC control chip via a second bus (bus to chip 150), the first bus being connected to the second bus (via PCH chip 110).
Lee does not disclose a BMC chip and other related limitations. In the same field of art (peripheral configuration), Chen discloses a system to monitor the condition of a flash memory device such as flash memory devices that store hardware settings for a BIOS or system logs in a computer system (abstract). In one embodiment, Chen further discloses a basic input/output system (BIOS) system, comprising:
a second BIOS chip (fig. 1A, chip 134), configured to run a second BIOS sub-system (par. 27, BIOS image 150, 152…);
a baseboard management controller (BMC) chip (fig. 1B, BMC chip 132), configured to run a BMC program (par. 27, stores system logs 136...);
a BMC control chip (BMC 130), configured to control the BMC chip and the second BIOS chip (par. 26 “monitored by the BMC 130), the BMC control chip being connected to the BMC chip and the second BIOS chip (fig. 1A, 1B); and
a platform controller hub (PCH 116), configured to control the BMC control chip (par. 28), the platform controller hub being connected to the BMC control chip via a second bus (fig. 1B, bus 160, 162), and the platform controller hub being connected to a central processing unit (CPU) (CPU 112).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee and Chen in order to improve the reliability of the system (par. 8).
As to claim 2, Lee/Chen discloses the dual BIOS system according to claim 1, wherein an access entity of the dual BIOS system comprises a host (fig. 4 switch circuit 330) and the BMC control chip, and the host and the BMC control chip perform interactive access by transmitting instructions (par. 40).
As to claim 5, Lee/Chen discloses the dual BIOS system according to claim 2, wherein the BMC control chip transmits a sub-system switching request instruction to the host (Lee, par. 23 “transmits the first selection signal S1”) in response to the BMC control chip receiving a sub-system switching instruction (par. 23 “pass on the status”); and
the host switches from the first BIOS sub-system to the second BIOS sub-system in response to the host receiving the sub-system switching request instruction (par. 24 “connects the platform controller 100 to the memory 142”).
As to claim 6, Lee/Chen discloses the dual BIOS system according to claim 2, wherein the host switches from the first BIOS sub-system to the second BIOS sub-system in response to the host actively performing sub-system switching (Lee, par. 24 “connects the platform controller 100 to the memory 142”).
As to claim 7, Lee/Chen discloses the dual BIOS system according to claim 2, wherein the BMC control chip transmits a sub-system switching request instruction to the host in response to the BMC control chip detecting an operating system boot failure (Lee, par. 24 “the booting of the device 100 fails”); and
the host switches from the first BIOS sub-system to the second BIOS sub-system in response to the host receiving the sub-system switching request instruction (par. 24 “booting of the electronic device 100 based on the BIOS in the memory 142).
Claim 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chen and further in view of Futral et al (US 20140040605).
As to claim 3, Lee/Chen discloses the dual BIOS system according to claim 2, but does not disclose the limitations in claim 3. In the same field of art (peripheral configuration), Futral discloses a data processing system may comprise a primary basic input/output system (BIOS) image in a primary BIOS region and a rollback BIOS image in a rollback BIOS region (abstract). In one embodiment, Futral discloses that, after performing sub-system flash on a first BIOS chip (2A-C, step 334), a controller transmits a sub-system switching request instruction to a host (s336, “set BIOS update flag”), the host switches from the first BIOS sub-system to the second BIOS sub-system in response to the host receiving the sub-system switching request instruction (s320 to s420 “Primary BIOS authentic?”), the controller flashes the second BIOS sub-system on the second BIOS chip in response to a currently running BIOS sub-system being switched from the first BIOS sub-system to the second BIOS sub-system (s430, “copy primary BIOS to rollback partition”), the controller transmits the sub-system switching request instruction to the host in response to flash of the second BIOS sub-system on the second BIOS chip being completed (s432 “clear Rollback flag”) and the host switches from the second BIOS sub-system to the first BIOS sub-system in response to the host receiving the sub-system switching request instruction (s436 to s112). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Chen and Futral, by comprising: wherein after performing sub-system flash on the first BIOS chip, the BMC control chip transmits a sub-system switching request instruction to the host; the host switches from the first BIOS sub-system to the second BIOS sub-system in response to the host receiving the sub-system switching request instruction; the BMC control chip flashes the second BIOS sub-system on the second BIOS chip in response to a currently running BIOS sub-system being switched from the first BIOS sub-system
to the second BIOS sub-system; the BMC control chip transmits the sub-system switching request instruction to the host in response to flash of the second BIOS sub-system on the second BIOS chip being completed; and the host switches from the second BIOS sub-system to the first BIOS sub-system in
response to the host receiving the sub-system switching request instruction.
The motivation is to improve the reliability of the system (par. 11).
As to claim 4, Lee/Chen discloses the dual BIOS system according to claim 2, but does not disclose the limitations in claim 4. In the same field of art (peripheral configuration), Futral discloses a data processing system may comprise a primary basic input/output system (BIOS) image in a primary BIOS region and a rollback BIOS image in a rollback BIOS region (abstract). In one embodiment, Futral discloses that, after performing sub-system flash on the first BIOS sub-system on the first BIOS chip (fig. 2A-C, s334 “update primary BIOS”) , the host switches from the first BIOS sub-system to the second BIOS sub-system (s336 “set BIOS Update flag”), the host flashes the second BIOS sub-system on the second BIOS chip () in response to a currently running BIOS sub-system being switched from the first BIOS sub-system to the second BIOS sub-system (s430), and the host switches from the second BIOS sub-system to the first BIOS sub-system (s112 use primary partition) in response to flash of the second BIOS sub-system on the second BIOS chip being completed (s432 “clear rollback flag”, s433 “clear the BIOS update”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Chen and Futral, by comprising wherein after performing sub-system flash on the first BIOS sub-system on the first BIOS chip, the host switches from the first BIOS sub-system to the second BIOS sub-system; the host flashes the second BIOS sub-system on the second BIOS chip in response to a currently running BIOS sub-system being switched from the first BIOS sub-system to the second BIOS sub-system; and the host switches from the second BIOS sub-system to the first BIOS sub-system in response to flash of the second BIOS sub-system on the second BIOS chip being completed.
The motivation is to improve the reliability of the system (par. 11).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chen and further in view of Wang et al (US 20080288767, Wang).
As to claim 8, Lee/Chen discloses the dual BIOS system according to claim 2, wherein the host reads data from the first BIOS chip in response to the host operating normally (Lee, par. 23, “operates normally”);
the host transmits a data read instruction to the BMC control chip (par. 33. Note: It requires a read instruction to “boots the device 300 based on the BIOS in memory 342”);
the BMC control chip transmits data from the second BIOS chip to the host in response to the BMC control chip receiving the data read instruction (par. 33).
Lee/Chen does not disclose other limitations in claim 8. In the same field of art (peripheral configuration), Wang discloses a computer system with a function of automatically restoring, updating a BIOS (par. 8). In one embodiment, Wang discloses a host performs data check on the data from the first BIOS chip (s510) and the data from the second BIOS chip (s512) and performs data synchronization on the first BIOS chip and the second BIOS chip based on a data check result (s511, s513). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Chen and Wang, by configuring the host to perform data check on the data from the first BIOS chip and the data from the second BIOS chip and to perform data synchronization on the first BIOS chip and the second BIOS chip based on a data check result. The motivation is to improve the reliability of the system (par 7).
Allowable Subject Matter
Claims 9-18, 34-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/D.P/Examiner, Art Unit 2184