Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending.
Claim Objections
Claim 11 is objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim cannot depend from any other multiple dependent claim. See MPEP § 608.01(n). Accordingly, the claim 11 has not been further treated on the merits. Claim 11 is dependent upon claim 3, which is also a multiple dependent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (US20220397953, “Wang”).
As to claim 1, 12:
Wang teaches a controller for a memory (system 110; Fig .1), associated control method of operation (method of operation performed by memory system; Abstract, 0107-0112; Fig. 7); comprising:
a slot control determination logic (memory controller ; 0066, 0068, 0070), configured to acquire slot configuration information for defining a slot control mode, the slot control mode indicating a switching mode between a working mode and a power-down mode in each control cycle of a target memory (Fig. 3 shows sending of a mode signal 310, which is a signal for the memory system to transition between power modes; 0066, first power mode is a normal/active mode, second power mode is a power saving mode, and third power mode is a sleep/hibernate mode; 0068, 0070, 0072);
a command buffer, configured to cache access requests to the target memory in the power-down mode of the target memory (command queue 260 stores commands received in any power mode; 0044, 0046, 0048; commands may be received while operating in second [power saving] power mode; 0080, 0104) and
a low-power control logic, configured to control the target memory according to the slot control mode, so that the target memory enters a low-power state in the power-down mode and processes the access requests in the working mode (power management component controls what mode memory operates; 0093, 0094, 0097; upon receiving memory requests when in second [power saving] mode, memory device may transition to first power mode to process the command; 0080).
As to claim 2:
Wang teaches the slot configuration information comprises at least one of a number of power-down slots (mode signal 310, which is a signal for the memory system to transition between power modes; 0066, first power mode is a normal/active mode, second power mode is a power saving mode, and third power mode is a sleep/hibernate mode; 0068, 0070, 0072), a number of working slots, or a slot unit.
As to claim 10:
Wang teaches the slot control determination logic is further configured to control sending a refresh instruction to the target memory during a working slot to instruct the target memory to perform a refresh operation (perform memory refresh operation; 0022, 0023, 0062).
As to claim 11:
Wang a chip system, comprising a target memory and the controller (memory system having memory 130 and controller 115; Fig .1; also see rejection to claim 1).
Allowable Subject Matter
Claims 3-9 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3/13, the prior art teaches the memory operating in 3 different power modes but fails to suggest slot control mode comprises one of: a first control mode, in which each of a number of power-down slots, a number of working slots, and a slot unit is set to a respective fixed value; a second control mode, in which each of the number of the power-down slots and the slot unit is set to a respective fixed value, and the number of the working slots is configured to be adaptive and dependent on a number of the access requests to the target memory that are cached by the command buffer in a control cycle; or a third control mode, in which the slot unit is configured as a fixed value, and the command buffer has a first watermark, a first watermark timeout, a second watermark and a second watermark timeout, wherein the target memory is in the power-down mode when the number of the access requests in the command buffer is less than the first watermark and a duration exceeds the first watermark timeout, and the target memory is in the working mode when the number of the access requests in the command buffer is greater than the second watermark and the duration exceeds the second watermark timeout, wherein the first watermark is less than the second watermark.
Claims 4-9 and 14 are allowable for incorporating the limitations of claim 3/13, and further limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20150242141 teaches a method of storing data in a memory with many modes of power consumption.
US20200264788 discloses a system and method for memory power management that can change memory power mode during wake up events.
US20250013390 teaches a method for adjusting a working state of a memory device by changing the memory device to a power-down mode to reduce power consumption.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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