DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2025 has been placed in record and considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang, Yue-Wen (CN 113870812 A hereinafter Wang).
Referring to claim 1, Wang discloses a method comprising:
receiving a wakeup event at a system processor (Fig. 1; MIPI) (Wang- highlighted section; In one application scene, as shown in FIG. 5, when the MIPI data is sent, it will enter the data transmission preparation state, namely, from the data transmission state into the data transmission preparation state. after the MIPI enters the data sending preparation state, when reaching the preset standby time, for example, 60ms, if there is no data to be sent, then entering the idle state, namely, sending the preparation state from the data to the idle state. after the MIPI enters the idle state, if the AP needs to transmit data to the DDIC, then sending the awakening instruction to the MIPI, awakening the MIPI, making the MIPI enter the data sending state from the idle state, in the state of sending the data, sending data to the DDIC through MIPI, when the MIPI finishes the data transmission, then re-entering the data sending preparation state.);
waking the system processor (Fig. 1; MIPI) from an idle state to an active state (Wang- highlighted section; In one application scene, as shown in FIG. 5, when the MIPI data is sent, it will enter the data transmission preparation state, namely, from the data transmission state into the data transmission preparation state. after the MIPI enters the data sending preparation state, when reaching the preset standby time, for example, 60ms, if there is no data to be sent, then entering the idle state, namely, sending the preparation state from the data to the idle state. after the MIPI enters the idle state, if the AP needs to transmit data to the DDIC, then sending the awakening instruction to the MIPI, awakening the MIPI, making the MIPI enter the data sending state from the idle state, in the state of sending the data, sending data to the DDIC through MIPI, when the MIPI finishes the data transmission, then re-entering the data sending preparation state.); and
sending a wakeup signal during the waking of the system processor (Fig. 1; MIPI) at an output (Fig. 1; DDIC) of the system processor (Fig. 1; MIPI), the output being configured to be coupled to a display panel, the wakeup signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 2, Wang discloses further comprising: generating a new frame at the system processor; and sending the new frame from the system processor to the display panel after sending the wakeup signal (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 3, Wang discloses wherein the generating the new frame is performed by a display processor unit of the system processor and wherein the sending the new frame comprises sending the new frame from the display processor unit signal (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 4, Wang discloses wherein the display panel is in an idle state with the idle frame rate before the receiving the wakeup signal (Wang- highlighted section; Because in the actual application, it can through monitoring the MIPI working state from the data sending state into the idle state, adjusting display screen to refresh the frame rate of the image display, namely, the working state of the MIPI is in the idle state, reducing the display screen for image display refresh frame rate, the refresh frame rate of the display screen for image display is kept at a low refresh frame rate, and after the working state of the MIPI enters the data transmission state from the idle state, for example, the AP sends image data to the DDIC, because the DDIC will receive the image data, therefore, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display, without the need of monitoring whether the working state of the MIPI from the idle state into the data transmission state.).
Referring to claim 5, Wang discloses wherein the display panel repeatedly displays a same image at the idle frame rate (Wang- highlighted section; Because in the actual application, it can through monitoring the MIPI working state from the data sending state into the idle state, adjusting display screen to refresh the frame rate of the image display, namely, the working state of the MIPI is in the idle state, reducing the display screen for image display refresh frame rate, the refresh frame rate of the display screen for image display is kept at a low refresh frame rate, and after the working state of the MIPI enters the data transmission state from the idle state, for example, the AP sends image data to the DDIC, because the DDIC will receive the image data, therefore, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display, without the need of monitoring whether the working state of the MIPI from the idle state into the data transmission state.).
Referring to claim 9, Wang discloses wherein the sending the wakeup signal is performed independent of and parallel with the waking the system processor (Fig. 1; MIPI) (Wang- highlighted section; In one application scene, as shown in FIG. 5, when the MIPI data is sent, it will enter the data transmission preparation state, namely, from the data transmission state into the data transmission preparation state. after the MIPI enters the data sending preparation state, when reaching the preset standby time, for example, 60ms, if there is no data to be sent, then entering the idle state, namely, sending the preparation state from the data to the idle state. after the MIPI enters the idle state, if the AP needs to transmit data to the DDIC, then sending the awakening instruction to the MIPI, awakening the MIPI, making the MIPI enter the data sending state from the idle state, in the state of sending the data, sending data to the DDIC through MIPI, when the MIPI finishes the data transmission, then re-entering the data sending preparation state.).
Referring to claim 10, Wang discloses wherein the idle state of the system processor is a power collapse state (Wang- highlighted section; For example, when monitoring the MIPI working state from the data sending state into the idle state, reducing the display screen for image display refresh frame rate, so that when the AP does not send data to the DDIC, actively reducing the refresh frame rate of the display screen, so as to reduce the power consumption of the display screen. and when the working state of the MIPI enters the idle state from the data sending state, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display. That is, it does not need to monitor whether the working state of the MIPI enters the idle state from the data transmission state.).
Referring to claim 11, Wang discloses an apparatus comprising:
a system processor (Fig. 1; MIPI) configured to receive a wakeup event, the system processor configured to wake from an idle state to an active state in response to the wakeup event (Wang- highlighted section; In one application scene, as shown in FIG. 5, when the MIPI data is sent, it will enter the data transmission preparation state, namely, from the data transmission state into the data transmission preparation state. after the MIPI enters the data sending preparation state, when reaching the preset standby time, for example, 60ms, if there is no data to be sent, then entering the idle state, namely, sending the preparation state from the data to the idle state. after the MIPI enters the idle state, if the AP needs to transmit data to the DDIC, then sending the awakening instruction to the MIPI, awakening the MIPI, making the MIPI enter the data sending state from the idle state, in the state of sending the data, sending data to the DDIC through MIPI, when the MIPI finishes the data transmission, then re-entering the data sending preparation state.); and
a wakeup connector (Fig. 1; DDIC) coupled to the system processor (Fig. 1; MIPI) and configured to be coupled to a display panel (Fig. 1; Display panel) to send a wakeup signal to the display panel during the waking of the system processor (Fig. 1; MIPI) from the idle state, the wakeup signal being a command to the display panel to increase a frame rate of the display panel from an idle frame rate to an active frame rate (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 12, Wang discloses wherein the system processor is further configured to generate a new frame and to send the new frame to the display panel after sending the wakeup signal (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 13, Wang discloses wherein the system processor comprises a display processor unit wherein the display processor unit is configured to generate the new frame (Wang- highlighted section; because the working state of the MIPI enters the data sending state from the idle state, and not necessarily because the AP needs to send image data to the DDIC, and it is possible that the AP needs to send the control instruction of the screen display to the DDIC, for example, controlling the display voltage of the display screen control instruction and so on, therefore, Optionally, in some embodiments of the present application, can be monitored to the working state of the MIPI from the idle state into the data transmission state, and the MIPI data is image data, increasing the refresh frame rate of the display screen for image display.).
Referring to claim 14, Wang discloses wherein the system processor comprises an application processor and a display processor unit (Wang- highlighted section; shown in FIG. 1, AP terminal firstly through application program (Application, App) for layer rendering rendering, then through Surface Flinger performs layer synthesis to the drawn layer to obtain the image data, so as to send the image data to the DDIC through the mobile industry processor interface (MIPI). The DDIC stores the image data displayed by the AP in the buffer, and the image data in the buffer is scanned (read), and the control panel performs image refresh display (Display). under the high refresh frame rate display scene, AP terminal high frequency generates image data, correspondingly, the Panel side performs high frequency image refresh according to the image data, so as to improve the smoothness of the picture.).
Referring to claim 15, Wang discloses wherein the display panel is in an idle state with the idle frame rate before increasing the frame rate (Wang- highlighted section; For example, when monitoring the MIPI working state from the data sending state into the idle state, reducing the display screen for image display refresh frame rate, so that when the AP does not send data to the DDIC, actively reducing the refresh frame rate of the display screen, so as to reduce the power consumption of the display screen. and when the working state of the MIPI enters the idle state from the data sending state, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display. That is, it does not need to monitor whether the working state of the MIPI enters the idle state from the data transmission state.).
Referring to claim 16, Wang discloses wherein the system processor is configured to
avoid generating new frames in the idle state (Wang- highlighted section; For example, when monitoring the MIPI working state from the data sending state into the idle state, reducing the display screen for image display refresh frame rate, so that when the AP does not send data to the DDIC, actively reducing the refresh frame rate of the display screen, so as to reduce the power consumption of the display screen. and when the working state of the MIPI enters the idle state from the data sending state, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display. That is, it does not need to monitor whether the working state of the MIPI enters the idle state from the data transmission state.).
Referring to claim 20, Wang discloses wherein the idle state of the system processor is a power collapse state (Wang- highlighted section; For example, when monitoring the MIPI working state from the data sending state into the idle state, reducing the display screen for image display refresh frame rate, so that when the AP does not send data to the DDIC, actively reducing the refresh frame rate of the display screen, so as to reduce the power consumption of the display screen. and when the working state of the MIPI enters the idle state from the data sending state, after receiving the image data by the DDIC, automatically increasing the refresh frame rate of the display screen for image display. That is, it does not need to monitor whether the working state of the MIPI enters the idle state from the data transmission state.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Yue-Wen (CN 113870812 A hereinafter Wang) in view of Kernahan, Kent (CN 101505102 A hereinafter Kernahan).
Referring to claim 6, Wang as applied above does not specifically disclose further comprising receiving an input from at least one of a camera, a button, or an inertial reference system and wherein the receiving the wakeup event is in response to the receiving the input.
In an analogous art, Kernahan discloses further comprising receiving an input from at least one of a camera, a button, or an inertial reference system and wherein the receiving the wakeup event is in response to the receiving the input (Kernahan - highlighted section; a programmable keyboard scanning function in the central processing module (SYS-ID) 1205, the key is pressed to awaken from standby state keyboard scanning circuit, allowing scanning or detecting a single key. monitor function executed by software in central processing module (SYS) 1205, and provides the function of the monitor timer function. monitor timer functions may be used for software fault processing system. such as an external processor operating system (e.g., WinCE) operating complex may periodically temporarily maintained ("switching") specified signal on pin. whenever the designated signal pin is switched, the monitor timer reset the number. when the software of the host microprocessor is in fault, such that the specified pin is the signal is not switched in a predetermined time, then the predetermined program for executing the set of actions to recover at the external system processor operation. These actions include simply reset processor or other circuit element, or the processor cycling power off and on. cold starting (power-cycling) eliminates the current from the parasitic SCR, which may occur in the processor or other integrated circuit so as to influence recovery from semiconductor locking state. it also can correct typically utilizes logic or other abnormal reset signal can not be recovered through cold starting.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Kernahan to the system of Wang in order to allow a power supply capable of supplying different level voltage precision and is reliable.
Referring to claim 7, Wang as applied above does not specifically disclose wherein the sending the wakeup signal comprises setting a level on a pin of the system processor that is coupled to a hardware connection between the system processor and the display panel..
In an analogous art, Kernahan discloses wherein the sending the wakeup signal comprises setting a level on a pin of the system processor that is coupled to a hardware connection between the system processor and the display panel (Kernahan- highlighted section; a programmable keyboard scanning function in the central processing module (SYS-ID) 1205, the key is pressed to awaken from standby state keyboard scanning circuit, allowing scanning or detecting a single key. monitor function executed by software in central processing module (SYS) 1205, and provides the function of the monitor timer function. monitor timer functions may be used for software fault processing system. such as an external processor operating system (e.g., WinCE) operating complex may periodically temporarily maintained ("switching") specified signal on pin. whenever the designated signal pin is switched, the monitor timer reset the number. when the software of the host microprocessor is in fault, such that the specified pin is the signal is not switched in a predetermined time, then the predetermined program for executing the set of actions to recover at the external system processor operation. These actions include simply reset processor or other circuit element, or the processor cycling power off and on. cold starting (power-cycling) eliminates the current from the parasitic SCR, which may occur in the processor or other integrated circuit so as to influence recovery from semiconductor locking state. it also can correct typically utilizes logic or other abnormal reset signal can not be recovered through cold starting.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Kernahan to the system of Wang in order to allow a power supply capable of supplying different level voltage precision and is reliable.
Referring to claim 17, Wang as applied above does not specifically disclose further comprising at least one of a camera, a button, or an inertial reference system, and wherein the wakeup event is in response to an input from at least one of the camera, the button, or the inertial reference system.
In an analogous art, Kernahan discloses further comprising at least one of a camera, a button, or an inertial reference system, and wherein the wakeup event is in response to an input from at least one of the camera, the button, or the inertial reference system (Kernahan - highlighted section; a programmable keyboard scanning function in the central processing module (SYS-ID) 1205, the key is pressed to awaken from standby state keyboard scanning circuit, allowing scanning or detecting a single key. monitor function executed by software in central processing module (SYS) 1205, and provides the function of the monitor timer function. monitor timer functions may be used for software fault processing system. such as an external processor operating system (e.g., WinCE) operating complex may periodically temporarily maintained ("switching") specified signal on pin. whenever the designated signal pin is switched, the monitor timer reset the number. when the software of the host microprocessor is in fault, such that the specified pin is the signal is not switched in a predetermined time, then the predetermined program for executing the set of actions to recover at the external system processor operation. These actions include simply reset processor or other circuit element, or the processor cycling power off and on. cold starting (power-cycling) eliminates the current from the parasitic SCR, which may occur in the processor or other integrated circuit so as to influence recovery from semiconductor locking state. it also can correct typically utilizes logic or other abnormal reset signal can not be recovered through cold starting.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Kernahan to the system of Wang in order to allow a power supply capable of supplying different level voltage precision and is reliable.
Referring to claim 18, Wang as applied above does not specifically disclose wherein the wakeup connector is coupled to a dedicated pin of the system processor and wherein sending the wakeup signal comprises setting a level on the dedicated pin of the system processor between the system processor and the display panel.
In an analogous art, Kernahan discloses wherein the wakeup connector is coupled to a dedicated pin of the system processor and wherein sending the wakeup signal comprises setting a level on the dedicated pin of the system processor between the system processor and the display panel (Kernahan- highlighted section; a programmable keyboard scanning function in the central processing module (SYS-ID) 1205, the key is pressed to awaken from standby state keyboard scanning circuit, allowing scanning or detecting a single key. monitor function executed by software in central processing module (SYS) 1205, and provides the function of the monitor timer function. monitor timer functions may be used for software fault processing system. such as an external processor operating system (e.g., WinCE) operating complex may periodically temporarily maintained ("switching") specified signal on pin. whenever the designated signal pin is switched, the monitor timer reset the number. when the software of the host microprocessor is in fault, such that the specified pin is the signal is not switched in a predetermined time, then the predetermined program for executing the set of actions to recover at the external system processor operation. These actions include simply reset processor or other circuit element, or the processor cycling power off and on. cold starting (power-cycling) eliminates the current from the parasitic SCR, which may occur in the processor or other integrated circuit so as to influence recovery from semiconductor locking state. it also can correct typically utilizes logic or other abnormal reset signal can not be recovered through cold starting.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Kernahan to the system of Wang in order to allow a power supply capable of supplying different level voltage precision and is reliable.
Referring to claim 19, Wang as modified by Kernahan discloses herein the dedicated pin is a general purpose input/output pin (Kernahan - highlighted section; a programmable keyboard scanning function in the central processing module (SYS-ID) 1205, the key is pressed to awaken from standby state keyboard scanning circuit, allowing scanning or detecting a single key. monitor function executed by software in central processing module (SYS) 1205, and provides the function of the monitor timer function. monitor timer functions may be used for software fault processing system. such as an external processor operating system (e.g., WinCE) operating complex may periodically temporarily maintained ("switching") specified signal on pin. whenever the designated signal pin is switched, the monitor timer reset the number. when the software of the host microprocessor is in fault, such that the specified pin is the signal is not switched in a predetermined time, then the predetermined program for executing the set of actions to recover at the external system processor operation. These actions include simply reset processor or other circuit element, or the processor cycling power off and on. cold starting (power-cycling) eliminates the current from the parasitic SCR, which may occur in the processor or other integrated circuit so as to influence recovery from semiconductor locking state. it also can correct typically utilizes logic or other abnormal reset signal can not be recovered through cold starting.).
Claim Objections
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the display panel comprises a command mode display panel and wherein sending the wakeup signal comprises setting a general purpose input/output pin of a command mode interface of the display panel through the hardware connection”.
Conclusion
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/SCOTT D AU/Examiner, Art Unit 2624
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