Prosecution Insights
Last updated: October 26, 2026
Application No. 19/146,589

QUANTUM COMPUTER AND SINGLE-ELECTRON/SINGLE-HOLE TRANSPORTING METHOD

Non-Final OA §103
Filed
Jul 09, 2025
Priority
Mar 02, 2023 — nonprovisional of PCTJP2023007794
Examiner
CHEN, SIBIN
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
902 granted / 1041 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
20 currently pending
Career history
1066
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
44.2%
+4.2% vs TC avg
§102
38.8%
-1.2% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1041 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 5, 8, 9, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunne (PCT/EP2021/087073) in view of Pioro-Ladriere (US 2010/0270534). Regarding claim 1, fig. 1, 3, 4, and 6 of Kunne discloses a quantum computer comprising: a gate electrode array [102, 103, 104] disposed on a semiconductor base [10]; a single-electron manufacturing unit [e.g. that controlling the gates of fig. 4 for transporting the electron] (par. 17) for extracting a single electron; and an electron transport path [4, which are shuttling lanes] including a branch and serving as a transport path of the single electron in the semiconductor base, wherein a path as a branch destination of the single electron is selected by controlling the gate electrode array. Kunne does not disclose where the semiconductor base is a crystal one. However, par. 6 of Pioro-Ladriere describes a quantum device with a semiconductor crystal substrate. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the crystal substrate as taught in Pioro-Ladriere for the purpose of utilizing a suitable and well-known type of semiconductor substrate. Regarding claim 2, the combination as indicated above discloses wherein a path as a branch destination of the single electron is selected by synchronously applying at least two kinds of voltages to a gate electrode just before the branch to which the single electron moves and a gate electrode immediately after the branch (fig. 4 and 6 show voltage application to transport the electron). Regarding claim 5, the combination as indicated above discloses wherein a path as a branch destination of the single electron is selected by synchronously applying at least two kinds of voltages to a gate electrode in the position of the branch to which the single electron moves and a gate electrode immediately after the branch (fig. 4 and 6 show voltage application to transport the electron). Regarding claim 8, fig. 1, 3, 4, and 6 of Kunne discloses a quantum computer comprising: a gate electrode array [102, 103, 104] disposed on a semiconductor base [10]; a single-hole manufacturing unit [e.g. that controlling the gates of fig. 4 for transporting the hole] (par. 17) for extracting a single hole; and a hole transport path [4, which are shuttling lanes] including a branch and serving as a transport path of the single hole in the semiconductor base, wherein a path as a branch destination of the single hole is selected by controlling the gate electrode array. Kunne does not disclose where the semiconductor base is a crystal one. However, par. 6 of Pioro-Ladriere describes a quantum device with a semiconductor crystal substrate. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the crystal substrate as taught in Pioro-Ladriere for the purpose of utilizing a suitable and well-known type of semiconductor substrate. Regarding claim 9, the combination as indicated above discloses wherein a path as a branch destination of the single hole is selected by synchronously applying at least two kinds of voltages to a gate electrode just before the branch to which the single hole moves and a gate electrode immediately after the branch (fig. 4 and 6 show voltage application to transport the hole). Regarding claim 12, the combination as indicated above discloses wherein a path as a branch destination of the single hole is selected by synchronously applying at least two kinds of voltages to a gate electrode in the position of the branch to which the single hole moves and a gate electrode immediately after the branch (fig. 4 and 6 show voltage application to transport the hole). Regarding claim 15, this claim is merely a method to operate the circuit having structure recited in claims 1, 2, 5, 8, 9, and 12. Since Kunne in view of Pioro-Ladriere above teaches the structure, the method to operate such a circuit is similarly disclosed. Allowable Subject Matter Claims 3, 4, 6, 7, 10, 11, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Levonian describes a protocol for optically entangling distinguishable qubits. Cohen describes a quantum processor with quantum programming field payloads. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jul 09, 2025
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750051
BOOTSTRAP CIRCUIT
2y 7m to grant Granted Sep 29, 2026
Patent 12738901
ACTIVE BALUN AMPLIFIER
2y 8m to grant Granted Sep 15, 2026
Patent 12732100
FRACTIONAL CHARGE PUMP CONVERTERS
2y 7m to grant Granted Sep 08, 2026
Patent 12712553
GAIN CALIBRATION OF DIGITAL-TO-TIME CONVERTER (DTC) USED IN FRACTIONAL FREQUENCY DIVIDERS
1y 7m to grant Granted Aug 18, 2026
Patent 12700800
MULTI-FUNCTION HIGH SIDE FIELD-EFFECT TRANSISTOR DRIVER CIRCUIT
2y 9m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.2%)
2y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1041 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month