Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 objected to because of the following informalities: in the limitation “the payload structure value is configured to represents a component that generates error information in the specified processor,”. “is configured to” should be followed by a verb in its base form, like “represent”. The word “represents” is a third person present, which acts on a third person singular subject(the payload structure value), so if you want to keep “represents”, then take out “is configured to”; so the limitation should either be “the payload structure value represents a component”, or if you want to keep “is configured to” the limitation should be “the payload structure value is configured to represent a component”. Appropriate correction is required. For the purposes of examination, claim 1 will be interpreted as “the payload structure value is configured to represent a component”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8,10,12-17,21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220318087 A1 (Hong) in view of TW 201715396 A (Huang), US 20240232110 A1 (Som), and US 20060085690 A1 (Bolen).
Regarding claim 1, Hong teaches,
A method for processing processor information, comprising:
reading, by a baseboard management controller on a target device(par 6 – teaches using a baseboard management controller (BMC) to retrieve error data from MCA registers. fig 3:139; par 48– teaches the processor 101 logging errors and communicating the error event details to a BMC 139, which stores the error event details into a storage device.), a register value of a specified register, wherein the specified register is located in a specified processor of the target device, and the specified register is a register configured to store, according to the register value, error information generated by a set of components in the specified processor;(fig 4:165; par 6,54 – teaches how in step 165, the processor writes the error data into the registers.)
converting, by the processor, a read target register value according to a set of specified parameters to obtain a target converted result, wherein the set of specified parameters are parameters used to perform error information converting;(fig 4:167-169; par 55 – teaches how the error data can be in an encoded format, for example following the predefined specification of Machine Check Architecture (MCA); par 59 – teaches how the processor generates second data(e.g., error log 127, error event details 143) about the error based on the error data that was stored in the registers.) and
recording the target converted result into a system event log of the baseboard management controller(par 60 – teaches storing the generated second data at a location not affected by restarting the operating system of the system having errors. par 63 – lists possible locations for the storage location, including the BMC 139. par 48 – teaches error event details being communicated to the BMC, where the BMC then stores the error event details in a storage device controlled by the BMC.) in a case where it is determined, according to the target converted result, that at least one component in the specified processor has generated error information; (fig 4:161, 171; par 51, 53-56 – teaches detecting an error in a memory module or other hardware component, and triggering the process shown in figure 4, where the converted result is eventually stored in the BMC.)
wherein the reading, by a baseboard management controller on a target device(fig 1:103; par 34, 6 – teaches a BMC that monitors devices and retrieves error data from MCA registers in response to hardware errors, storing the error data in a storage area of the BMC for subsequent error analysis diagnosis, etc.), a register value of a specified register comprises: reading, by the by the baseboard management controller, the register value of the specified register(par 35 – teaches how the BMC can operate autonomously and independently from the devices it monitors, and communicates with error handlers on the monitored devices about hardware errors using Intelligent Platform Management Interface (IPMI); par 6 “For example, in response to a hardware error in the server computer, a Baseboard Management Controller (BMC) configured on the motherboard of the server computer can monitor the error events in the microprocessor of the server computer, retrieve the error data from the MCA registers in response to a hardware error, and store the error data from MCA registers into a storage area of the Baseboard Management Controller (BMC) for subsequent error analysis, diagnosis, etc.”) via an integrated circuit bus.(fig 1:100; par 22 – teaches using an integrated circuit bus to communicate between components)
However, Hong focuses on having the processor do the converting instead of converting, by the baseboard management controller, a read target register value. Hong also does not teach limitations “the target converted result is character information corresponding to error information generated by the set of components in the specified processor; the BMC performs one-to-one converting of the data structure of the target register values according to system events, record numbers, and a payload structure value; the payload structure value is configured to represents a component that generates error information in the specified processor, a location in the component, and a type of the error;” and “the register value of the specified register via an integrated circuit bus having a specified clock frequency.”
On the other hand, Huang teaches,
converting, by the baseboard management controller, a read target register value according to a set of specified parameters to obtain a target converted result, wherein the set of specified parameters are parameters used to perform error information converting; (abstract, claim 1 – teaches a BMC with an error comparison table that links system error codes with system error messages, which the BMC uses to convert system error codes to system error messages. )
the target converted result is character information corresponding to error information generated by the set of components in the specified processor; the BMC performs one-to-one converting of the data structure of the target register values according to system events(abstract, claim 1 – teaches a BMC with an error comparison table that links system error codes with system error messages, which the BMC uses to convert system error codes to system error messages. )
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hong so that the BMC performs the conversion of the retrieved error register value into corresponding error message/character information, as taught by Huang. Hong teaches that error data stored in processor registers is decoded to generate error log/error event details and that the resulting error information may be preserved in a BMC for subsequent error analysis and diagnosis. Hong explains that storing the data in the BMC provides an out of band storage location that isn’t affected by the failing hardware or any restart operations of the failing hardware(Hong par 35,48). Huang teaches a known BMC-side error-code conversion technique in which the BMC stores an error comparison table recording relationships between system error codes and system error messages, receives a system error code, finds the corresponding system error message from the error comparison table, records the system error message, and outputs the system error message so that a user can quickly and directly know what error has occurred. A person of ordinary skill in the art would have been motivated to apply Huang’s BMC-side error-code-to-error-message conversion technique to Hong’s BMC-preserved processor error information in order to provide understandable diagnostic information from the BMC without requiring continued reliance on the failing host processor, BIOS, or operating system after a hardware error or restart. Such modification would have applied the known technique of storing an error-code/message mapping table in a BMC and using the BMC to convert received error codes into user-understandable error messages to the similar problem in Hong of preserving and analyzing processor error register information after hardware errors.
However, Hong and Huang does not explicitly teach “the BMC performs one-to-one converting of the data structure of the target register values according to system events, record numbers, and a payload structure value; the payload structure value is configured to represents a component that generates error information in the specified processor, a location in the component, and a type of the error;” and “the register value of the specified register via an integrated circuit bus having a specified clock frequency.”. Huang does, however, teach the BMC performs one-to-one converting of the data structure of the target register values according to system events(Huang abstract, claim 1)
On the other hand, Bolen teaches,
the viewing server performs event-record/payload structure of the target register values according to system events,(fig 2; par 22 – teaches that system event logging is done and presented to the user in a user readable format through the system event viewing server.) record numbers(fig 3; par 29,32,33,35 – teaches primary and secondary events that are linked by Generator ID and their sequential positioning, which serves as a record number. Hong par 19,29 – also teaches a timestamp of the error, and an error count of the hardware error event, identification/serial number of the module in which the hardware error occurs, etc.), and a payload structure value;(fig 2:24; par 26 – teaches three bytes of event data fields which provide additional information about the event; fig 3; par 5-6, 29-31 - teaches primary and secondary events. Primary events describe which device cause the error and secondary events provide information about the registers that contain error values or status data. ) the payload structure value is configured to represent a component that generates error information in the specified processor,(par 23– teaches a generator ID which describes the origin of the event. Par 31 – which teaches primary event records which describe which device caused the error and are related to secondary events, which contain error values or status data.) a location in the component,(par 27 – teaches how location/device identification details need to be logged. Par 35 teaches an event register pointer which ties secondary event to identifying information in the primary events, as well as register offsets to locate error information.) and a type of the error;(par 24 – teaches the event type field which contains data that describes the type and class of trigger for the event. )
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the error monitoring, processing, and storage system of Hong and Huang with Bolen’s error event-record structure.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because Bolen’s error event-record structure would have predictably improved Hong and Huang by organizing the error information into a standard system event log format. The combination would have involved applying a known technique taught by Bolen to the similar system of Hong and Huang to improve a similar system in a predictable way.
However, Hong, Huang, and Bolen does not specifically teach reading, … the register value of the specified register via an integrated circuit bus having a specified clock frequency.
On the other hand, Som teaches,
wherein the reading, by a baseboard management controller on a target device, a register value of a target data comprises: reading, by the baseboard management controller, the target data of the specified register via an integrated circuit bus having a specified clock frequency.(fig 3; par 52– teaches a timing diagram that illustrates how the bus width of the bus can be dynamically varied at different times to read different portions from memory; par 35-37, 41 – teaches a configuration register that stores bus parameters such as clock parameters and bus width parameters to be used to read certain data. Par 47,48 – teaches reading data using different bus clock frequencies. )
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Hong, Huang, and Bolen to incorporate the bus clock frequency parameter of Som. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Hong, Huang, and Bolen -- a need for how to properly set a bus clock frequency to adapt communication settings with different components -- with Som providing a known method to solve a similar problem. Som provides “In accordance with some implementations of the present disclosure, an attack mitigation engine is able to dynamically change fetch parameters that control communication attributes of a bus between a nonvolatile memory device that stores a target program code and a bus controller for the bus. By varying the communication attributes of the bus, portions of the target program code can be retrieved from the nonvolatile memory device in an unpredictable manner ( e.g., at different rates, in segments of different sizes, etc.), which affects the timing of delivering the portions of the target program code for execution on a processor.”(Som par 15). A person of ordinary skill in the art would have used Som’s configurable bus-clock technique to ensure that the BMC reads register/error information over the management bus using a controlled clock frequency compatible with the target device and suitable for reliable data transfer.
Regarding claim 2, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong and Huang further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1 – teaches a BMC with an error comparison table that links system error codes with system error messages, which the BMC uses to convert system error codes to system error messages.), a read target register value according to a set of specified parameters to obtain a target converted result(Hong fig 4:169; par 56, 59 - teaches a firmware error handler that performs blocks 169 and 171 and generates second data/error event details based on first error data stored in processor registers. ) comprises:
converting, by the baseboard management controller(Huang - abstract, claim 1), the read target register value by using a preset converting tool according to the set of specified parameters to obtain the target converted result, wherein the preset converting tool is a converting tool matching a data structure used by the specified register to perform data storage.(Hong par 55 - teaches first data/error data encoded according to a predefined MCA specification; fig 4:169,171; par 59 - teaches generating second data/error event details from the encoded error data in the registers.)
Regarding claim 3, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1), a read target register value according to a set of specified parameters to obtain a target converted result(par 25, 55 - teaches processor registers storing error data, such as MCA registers, and first error data encoded according to a predefined MCA specification) comprises:
converting, by the baseboard management controller(Huang - abstract, claim 1), a value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain converted results respectively corresponding to the each specified parameter, wherein the target converted result comprises the converted results respectively corresponding to the each specified parameter.(par 29, 43 - teaches decoding error data retrieved from registers to determine a physical memory address and generate error event details)
Regarding claim 4, Hong, Huang, Bolen, and Som teaches,
The method according to claim 3,
Hong further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1), a value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain converted results respectively corresponding to each specified parameter(par 19 – teaches firmware/OS instructions that collect and preserve comprehensive hardware-error data even after restart; par 55 – teaches MCA-encoded first error data) comprises:
in a case where the set of specified parameters comprises an event type parameter,(par 19 - teaches collecting hardware-error event count, address information, MCE classification, hardware-error type, configuration parameters, and memory-module identification/serial number)
converting, by the baseboard management controller(Huang - abstract, claim 1), a value of a first specified byte in the target register value to obtain target event type information, wherein the first specified byte is at least one byte corresponding to the event type parameter, and the event type parameter is a parameter corresponding to an event type of a system event which occurs in the specified processor.(par 29 - teaches decoding register error data to collect event count, address information, MCE classification, and hardware-error type)
Regarding claim 5, Hong, Huang, Bolen, and Som teaches,
The method according to claim 3,
Hong further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1), a value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain converted results respectively corresponding to each specified parameter(par 19 - teaches firmware/OS instructions that collect and preserve comprehensive hardware-error data even after restart; par 55 teaches MCA-encoded first error data) comprises:
in a case where the set of specified parameters comprises an event ID parameter, converting, by the baseboard management controller, a value of a second specified byte in the target register values to obtain a target event ID, wherein the second specified byte is at least one byte corresponding to a record number, a mapping relationship exists between the record number and the event ID parameter, and the event ID parameter is a parameter corresponding to an event ID corresponding to a system event which occurs in the specified processor.(par 47 - teaches error event details including memory-module and processor identification, event context, and operating conditions; par 19 - teaches timestamp, error count, address information, and memory-module identification/serial number )
Regarding claim 6, Hong, Huang, Bolen, and Som teaches,
The method according to claim 3,
Hong further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1), a value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain converted results respectively corresponding to each specified parameter(par 19 - teaches firmware/OS instructions that collect and preserve comprehensive hardware-error data even after restart; par 55 - teaches MCA-encoded first error data) comprises:
in a case where the set of specified parameters comprises an error information locating parameter, converting, by the baseboard management controller, a value of a third specified byte in the target register value to obtain target locating information, wherein the third specified byte is at least one byte corresponding to the error information locating parameter, and the error information locating parameter is a parameter configured to locate a source component of error information, an error location in the source component, and a type of the error information.(par 19 - teaches collecting hardware-error address information including memory module, bank group, bank, row/column, MCE classification, hardware-error type, configuration parameters, memory-module identification/serial number, and timing parameters.)
Regarding claim 7, Hong, Huang, Bolen, and Som teaches,
The method according to claim 6,
Hong further teaches,
wherein the error information locating parameter comprises a set of sub-locating parameters, and the set of sub-locating parameters comprises an error type parameter, an error subtype parameter and an error location parameter, wherein the error type parameter is configured to record the source component of the error information, the error subtype parameter is configured to record a source subcomponent in the source component of the error information, and the error location parameter is configured to record an error location where the error information occurs; (par 19 - teaches collecting hardware-error address information including memory module, bank group, bank, row/column, MCE classification, hardware-error type, configuration parameters, memory-module identification/serial number, and timing parameters)
in a case where the set of specified parameters comprises the error information locating parameter, the converting, by the baseboard management controller, a value of a third specified byte in the target register value to obtain target locating information(par 44, claim 4 - teaches decoding register error data to obtain physical memory address information, including row and column addresses) comprises:
in a case where the set of specified parameters comprises the error information locating parameter, sequentially converting, by the baseboard management controller, a value of at least one byte corresponding to each sub-locating parameter in the set of sub-locating parameters in the third specified byte in the target register value to obtain converted results respectively corresponding to the each sub-locating parameter, wherein the target locating information comprises the converted results respectively corresponding to the each sub-locating parameter. (par 19 - teaches hierarchical error-address information including memory module, bank group, bank, row/column, MCE classification, hardware-error type, configuration parameters, and identification/serial number. par 44, claim 4 - teaches decoding register error data to obtain physical memory address information, including row and column addresses)
Regarding claim 8, Hong, Huang, Bolen, and Som teaches,
The method according to claim 3,
Hong further teaches,
wherein the converting, by the baseboard management controller(Huang - abstract, claim 1), a value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain converted results respectively corresponding to each specified parameter(par 44, claim 4 - teaches decoded physical address information, including row/column addresses, from register error data) comprises:
searching, by the baseboard management controller, for converted tables respectively corresponding to the each specified parameter and converted results respectively corresponding to each specified parameter using the value of at least one byte corresponding to each specified parameter in the target register value,(par 43 - teaches decoding register error data to generate error event details) wherein the converted tables respectively corresponding to the each specified parameter is configured to record a correlation between a value corresponding to the each specified parameter stored in the specified register and a parameter value of the each specified parameter.(par 55 - teaches error data encoded according to a predefined MCA specification)
Regarding claim 10, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the specified register is in a specified component of the specified processor;( par 6,54 – teaches how in step 165, the processor writes the error data into the registers.)
Som further teaches,
before reading, by the baseboard management controller(fig 1:112, 106; par 16, 18 - teaches a bus controller that may be part of a BMC, target devices connected to the bus, and a bus as a communication link with signal lines for data transfer), the register value of the specified register via an integrated circuit bus having a specified clock frequency(par 52– teaches a timing diagram that illustrates how the bus width of the bus can be dynamically varied at different times to read different portions from memory; par 35-37, 41 – teaches a configuration register that stores bus parameters such as clock parameters and bus width parameters to be used to read certain data. Par 47,48 – teaches reading data using different bus clock frequencies.), the method further comprises:
setting a frequency of the integrated circuit bus via which the baseboard management controller communicates with the specified component to the specified clock frequency during initialization of the baseboard management controller. (par 35-37, 41, 46-48 - teaches a clock parameter that corresponds to bus clock frequency, a configuration register storing the clock parameter, a bus control engine controlling bus clock frequency based on the programmed parameter, and reading data over the bus at selected clock frequencies)
Regarding claim 12, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein during the running of the specified processor, the method further comprises:
updating, by the specified processor, the register value stored in the specified register in real time according to the error information generated by the set of components.(fig 4:165; par 54 - teaches processor writing error data into registers;)
Regarding claim 13, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the target register value and the target converted result are recorded together into the system event log of the baseboard management controller, and the target converted result is target character string information obtained by converting the target register value;(fig 4:171; par 60 - teaches storing generated second data/error log/error event details at a location unaffected by restarting the operating system)
after recording the target converted result into the system event log of the baseboard management controller,(fig 4:171; par 60) the method further comprises:
However, Hong does not specifically teach in response to an acquired fault information display request, displaying, by a specified display end, the target register value and the target character string information recorded in the system event log of the baseboard management controller.
On the other hand, Huang teaches,
in response to an acquired fault information display request, displaying, by a specified display end, the target register value and the target character string information recorded in the system event log of the baseboard management controller.(abstract, claim 1 – teaches a BMC with an error comparison table that links system error codes with system error messages, which the BMC uses to convert system error codes to system error messages. Claims (claim 6?) “According to the debugging method of claim 1, the substrate management controller of the motherboard is electrically connected to a display, and in the step (F), when the substrate management controller receives a video graphics conversion signal from the display As the message output request, the baseboard management controller converts the at least one system error message into at least one display signal for output to the display.”)
Regarding claim 14, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the specified register is in a system control processor component of the specified processor(par 38,34 - teaches processor 101/main processor and BMC monitoring/managing operations of the main processor; fig 4:165; par 25,54 - teaches processor writing error data into registers and processor registers configured to store error data, such as MCA registers), and the specified processor is a reduced instruction set computer processor. (par 77 - teaches a processing device may be a reduced instruction set computing (RISC) microprocessor or a processor implementing other instruction sets.)
Regarding claim 15, Hong, Huang, Bolen, and Som teaches,
The method according to claim 3,
Hong further teaches,
wherein values of different fields in the target register value correspond to different specified parameters in the set of specified parameters.(par 47 teaches error event details including memory-module and processor identification, event context, and operating conditions at the time of the event; par 19 - teaches hardware-error data fields including timestamp, error count, address information, and memory-module identification/serial number)
Regarding claim 16, Hong, Huang, Bolen, and Som teaches,
The method according to claim 6,
Hong further teaches,
wherein converting, by the baseboard management controller(Huang - abstract, claim 1), a value of a third specified byte in the target register value to obtain target locating information comprises:
converting, by the baseboard management controller, an acquired payload structure value of the specified register to obtain the target locating information.( par 47 teaches error event details including memory-module and processor identification, event context, and operating conditions. Par 19 - teaches hardware-error payload/location information including timestamp, error count, address information, and memory-module identification/serial number)
Regarding claim 17, Hong, Huang, Bolen, and Som teaches,
The method according to claim 6,
Hong further teaches,
wherein before converting, by the baseboard management controller(Huang - abstract, claim 1), a value of a third specified byte in the target register value, the method further comprises:
acquiring a 48-byte payload structure value as the value of the third specified byte.(par 29 - teaches decoding register error data to determine physical memory address information; par 19 - teaches collecting a comprehensive payload of error information including timestamp, error count, address information, MCE classification, hardware-error type, configuration parameters, memory-module identification/serial number, and timing parameters)
Regarding claim 21, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the target register value binary values for representing error information generated by a set of components in the specified processor, and different values correspond to different error types and error information.(par 29 teaches decoding register error data to identify physical memory address, MCE classification, and hardware-error type. Par 55 - teaches first error data encoded according to a predefined MCA specification)
Regarding claim 22, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein a parameter value of the specified parameters is character information corresponding to the binary register value. (par 29 - teaches decoding register error data to identify physical memory address, MCE classification, and hardware-error type. par 55 - teaches first error data encoded according to a predefined MCA specification)
Regarding claim 23, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the baseboard management controller (BMC) in an Advanced RISC Machine (ARM) processor architecture includes a converting tool therein to form a BMC code program, and synchronously parse, by means of the BMC code program, values of the specified register(par 70 - teaches instructions programmed to decode first data/error data stored in processor registers in response to a memory-module error) acquired via an Inter-Integrated Circuit (I2C)(par 22 - teaches processor, memory modules, data storage, and separate processor coupled via a bus, and identifies examples including an Inter-Integrated Circuit bus) and record same in an System Event Log (SEL) log of the baseboard management controller.(par 6 - teaches the BMC monitors microprocessor error events, retrieves error data from MCA registers, and stores the error data in BMC storage for later analysis/diagnosis)
Regarding claim 24, Hong, Huang, Bolen, and Som teaches,
The method according to claim 23,
Hong further teaches,
wherein values of different bytes in the target register value correspond to different specified parameters in the set of specified parameters and the acquired binary register values are converted by the BMC code program.(par 26 - teaches processor error data encoded for compact reporting and that decoding such data may require additional data; par 55 - teaches first error data encoded according to a predefined MCA specification. )
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220318087 A1 (Hong) in view of TW 201715396 A (Huang), US 20240232110 A1 (Som), and US 20060085690 A1 (Bolen) as applied to claim 1 above, and further in view of US 20090129186 A1 (Schnell).
Regarding claim 11, Hong, Huang, Bolen, and Som teaches,
The method according to claim 1,
Hong further teaches,
wherein the reading, by a baseboard management controller on a target device, a register value of a specified register(par 6, 34 – teaches BMC monitoring/managing the main processor, monitoring microprocessor error events, retrieving error data from MCA registers, and storing the data in BMC storage) comprises:
reading, by the baseboard management controller, the register value of the specified register in a responsive polling manner.( par 6 - teaches BMC monitoring microprocessor error events and retrieving MCA-register error data in response to a hardware error)
However, Hong, Huang, Bolen, and Som do not specifically teach reading, by the baseboard management controller, the register value of the specified register in a timed polling manner.
On the other hand, Schnell teaches,
wherein the reading, by a controller on a target device, a register value of a specified register(par 28) comprises:
reading, by the baseboard management controller, the register value of the specified register in a timed polling manner.(par 28 - teaches polling fail-signature data to perform self-diagnostics, continuing to poll periodically if no error is stored, and periodic polling at a predefined frequency)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Hong, Huang, Bolen, and Som to incorporate the polling frequency of Schnell. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Hong, Huang, Bolen, and Som -- a need for how to read errors in processors -- with Schnell providing a known method to solve a similar problem. Schnell provides “Embodiments of the invention may generally provide techniques that allow self-diagnosis of errors found in a multi-chip package (MCP). For example, for some embodiments, when an error is detected, information regarding the error can be stored in a non-volatile memory, which can be later read to determine characteristics regarding the error.”(Schnell par 14)
Response to Arguments
Applicant’s arguments, see remarks pg 8-12, filed 06/09/2026, with respect to the objections to claim 3,4,5,6,8,22,24 and the rejection of claims 1-8,10-17,21-24 under 35 U.S.C. 101 have been fully considered and are persuasive. The objections and rejections under 35 U.S.C. 101 of 03/09/2026 has been withdrawn.
Applicant’s arguments, see remarks pg 8-12, filed 06/09/2026, with respect to the rejection(s) of claim(s) 1-8,10,12-17,21-24 under 35 U.S.C. 103 as being unpatentable over US 20220318087 A1 (Hong) in view of US 20240345915 A1 (Liu) and US 20240232110 A1 (Som) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view 35 U.S.C. 103 as being unpatentable over US 20220318087 A1 (Hong) in view of TW 201715396 A (Huang), US 20060085690 A1 (Bolen), and US 20240232110 A1 (Som).
With respect to the independent claims, the applicant has argued that Hong, Liu, and Som does not teach limitations “reading, by a baseboard management controller on a target device, a register value of a specified register, wherein the specified register is located in a specified processor of the target device, and the specified register is a register configured to store, according to the register value, error information generated by a set of components in the specified processor;”. The examiner respectfully disagrees. Hong teaches limitation “reading, by a baseboard management controller on a target device, a register value of a specified register, wherein the specified register is located in a specified processor of the target device” in the cited (par 6 – teaches using a baseboard management controller (BMC) to retrieve error data from MCA registers. fig 3:139; par 48– teaches the processor 101 logging errors and communicating the error event details to a BMC 139, which stores the error event details into a storage device.) and teaches limitation “and the specified register is a register configured to store, according to the register value, error information generated by a set of components in the specified processor;” in the cited (fig 4:165; par 6,54 – teaches how in step 165, the processor writes the error data into the registers.). Under the broadest reasonable interpretation, this teaches or at least suggests the claimed “reading, by a baseboard management controller on a target device, a register value of a specified register, wherein the specified register is located in a specified processor of the target device, and the specified register is a register configured to store, according to the register value, error information generated by a set of components in the specified processor;”.
With respect to the independent claims, the applicant has argued that the combination of Hong, Liu, and Som does not teach limitations “converting, by the baseboard management controller, a read target register value according to a set of specified parameters to obtain a target converted result, wherein the set of specified parameters are parameters used to perform error information converting; the target converted result is character information corresponding to error information generated by the set of components in the specified processor; the BMC performs one-to-one converting of the data structure of the target register values according to system events”, explaining that Hong does the converting in the processor and Liu’s BMC only reads the already converted data. The newly cited Huang teaches in the cited (abstract, claim 1 – teaches a BMC with an error comparison table that links system error codes with system error messages, which the BMC uses to convert system error codes to system error messages.). Under the broadest reasonable interpretation, this new combination of Hong and Huang teaches or at least suggests the claimed “converting, by the baseboard management controller, a read target register value according to a set of specified parameters to obtain a target converted result, wherein the set of specified parameters are parameters used to perform error information converting; the target converted result is character information corresponding to error information generated by the set of components in the specified processor; the BMC performs one-to-one converting of the data structure of the target register values according to system events”.
With respect to the independent claims, the applicant has argued that Hong, Liu, and Som does not teach limitations “the BMC performs one-to-one converting of the data structure of the target register values according to system events, record numbers, and a payload structure value; the payload structure value is configured to represents a component that generates error information in the specified processor, a location in the component, and a type of the error;”. The newly cited Bolen teaches system events in the cited (fig 2; par 22 – teaches that system event logging is done and presented to the user in a user readable format through the system event viewing server.), record numbers in the cited (fig 3; par 29,32,33,35 – teaches primary and secondary events that are linked by Generator ID and their sequential positioning, which serves as a record number. Hong par 19,29 – also teaches a timestamp of the error, and an error count of the hardware error event, identification/serial number of the module in which the hardware error occurs, etc.), payload structure value in the cited (fig 2:24; par 26 – teaches three bytes of event data fields which provide additional information about the event; fig 3; par 5-6, 29-31 - teaches primary and secondary events. Primary events describe which device cause the error and secondary events provide information about the registers that contain error values or status data.), limitation “the payload structure value is configured to represent a component that generates error information in the specified processor” in the cited (par 23– teaches a generator ID which describes the origin of the event. Par 31 – which teaches primary event records which describe which device caused the error and are related to secondary events, which contain error values or status data.), a location in the component in the cited (par 27 – teaches how location/device identification details need to be logged. Par 35 teaches an event register pointer which ties secondary event to identifying information in the primary events, as well as register offsets to locate error information.), and a type of the error in the cited(par 24 – teaches the event type field which contains data that describes the type and class of trigger for the event.). Under the broadest reasonable interpretation, this combination teaches or at least suggests the claimed “the BMC performs one-to-one converting of the data structure of the target register values according to system events, record numbers, and a payload structure value; the payload structure value is configured to represents a component that generates error information in the specified processor, a location in the component, and a type of the error;”.
With respect to the independent claims, the applicant has argued that Som does not teach limitations “wherein the reading, by a baseboard management controller on a target device, a register value of a specified register comprises: reading, by the baseboard management controller, the register value of the specified register via an integrated circuit bus having a specified clock frequency.”. The examiner respectfully disagrees. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The rejection does not rely on Hong, Huang, or Bolen alone for the specified clock-frequency feature. Hong teaches the BMC retrieving processor error data from MCA registers and communicating error information using a bus in the cited (Hong par 34,6,35,22), and Som is relied upon for the known bus-clock-frequency aspect of the communication bus in the cited (Som par 52,35-37,41,47,48). Som teaches that the bus controller may be part of a BMC and that the bus may be an Inter-Integrated Circuit (I2C) bus(par 16,22). Som teaches that the bus attribute parameters include a clock parameter relating to a clock frequency of a bus clock signal, and that the clock parameter may be set to different values corresponding to different bus clock frequencies(par 35-37). Som teaches that the bus control engine controls the frequency of the bus clock signal based on the clock parameter programmed into the configuration register(par 41). Som teaches reading portions of data while the bus clock signal runs at different clock frequencies(par 47-48). Therefore, under the broadest reasonable interpretation, this teaches or at least suggests the claimed “wherein the reading, by a baseboard management controller on a target device, a register value of a specified register comprises: reading, by the baseboard management controller, the register value of the specified register via an integrated circuit bus having a specified clock frequency.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210326208 A1 - Liang - BIOS gathers error data from CPU and sends them to BMC for storage.
US 20230195568 A1 - Hong - BIOS gathers error data from CPU and sends them to BMC for storage.
US 20220171672 A1 - Mitra - CPU stores error data on registers, BMC reads it afterwards.
US 20210255939 A1 - Chaiken - Forensic data manager parses forensic data. Reads the MSR register
US 20220066861 A1 - Tan - BMC reads system on chip error registers and translates error codes.
US 20070061634 A1 - Marisetty - parses error and log data. See paragraph 63 " In a block 506, the OS parses multiple error sections to identify the corresponding CMCI/CPEI value and setting for each error structure. "
US 20190026239 A1 - Chalfant - machine check error storm events.
US 20240345915 A1 - Liu - BIOS gathers error data from PCIE devices, gathers extra data like Base Address Register (BAR) information, from error registers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.X./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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