DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/14/2025 was considered by the examiner.
Claim Objections
Claims 1-18 and 20-21 are objected to because of the following informalities: the terms “CXL” and “DRAM” are never spelled out throughout the claims. The first instance of an acronym must be spelled out in the claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 and 20-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1-18 and 20-21, the term CXL is never described, spelled out or explained throughout the claims or the specification. Although this might be a term of the art, it is not clear if the applicant intends this term to refer to an external device that expands memory capacity and speed using a Compute Express Link standard. As such, without knowing what is intended, the term renders the claims indefinite. Clarification is required.
Claim 5, the claimed “comparison table” renders the claim indefinite because it is not clear if applicant intends to refer to the translation table or if this is a different independent table.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malladi et al. [CN 113742256], Applicant Cited Art.
Claim 1, Malladi et al. discloses a CXL memory module, comprising a controller chip and at least one set of DRAM chips, wherein the controller chip has a CXL interface [discloses CXL memory modules 135 comprising controller 137 and DRAM 120, wherein the controller connects via CXL interface; Detailed description and Fig. 1A, 1C, 5], and the CXL memory module performs at least one of operations [controller performs memory operations and virtualization, Fig .10]: the CXL memory module running a virtual memory [performs address translation to present virtualized aggregation of memory, detailed description]; and the CXL memory module performing memory allocation [performs memory allocation across memory devices / partitions based on requests, detailed description].
Claim 2, Malladi et al. discloses the CXL memory module according to claim 1, wherein the CXL memory module runs the virtual memory, and the controller chip is configured to perform following operations [discloses controller 137 executing address translation and memory operations]: establishing a logical physical address translation table [maintains address translation tables mapping processor side to memory side addresses]; and receiving an operation instruction based on a logical address, translating the logical address into a physical address of a DRAM chip based on the logical physical address translation table, and performing an operation according to the physical address [receives read/write commands with host logical addresses, translates them using the table, and accesses DRAM].
Claim 3. Malladi et al. discloses the CXL memory module according to claim 2, wherein the CXL memory module supports reading by a plurality of main bodies, and the controller chip establishes one logical physical address comparison table for each main body [CXL modules are shared by a plurality of host/servers (main bodies), where isolated logical devices (LDs) maintain isolated address spaces/mapping per host]; and the controller chip receiving the operation instruction based on the logical address, translating the logical address into the physical address of the DRAM chip based on the logical physical address translation table, and performing the operation according to the physical address comprises: when receiving the operation instruction based on the logical address, finding a logical physical address comparison table corresponding to a main body according to a main body identification in the operation instruction, translating the logical address into the physical address of the DRAM chip according to the found logical physical address comparison table, and performing the operation on the DRAM chip according to the physical address [incoming transaction flits carry LD-IDs / host identifiers, the switch/controller routes and translates addresses using the mapping bound to that specific logical device / host].
Claim 4. Malladi et al. discloses the CXL memory module according to claim 2, wherein the controller chip receiving the operation instruction based on the logical address, translating the logical address into the physical address of the DRAM chip based on the logical physical address translation table, and performing the operation according to the physical address comprises: receiving a memory read instruction sent by a main body through a cxl.mem protocol, wherein the memory read instruction carries a target logical address of data to be read [cxl.mem memory read transactions carrying targeted target memory addresses from processing circuits]; translating the target logical address into a target physical address of the DRAM chip based on the logical physical address translation table [translates processor side address to memory side DRAM address]; and reading out corresponding data from the DRAM chip according to the target physical address and returning the corresponding data to the main body [reads requested data from DRAM location and returns response flits back to host].
Claim 5. Malladi et al. discloses the CXL memory module according to claim 2, wherein the controller chip receiving the operation instruction based on the logical address, translating the logical address into the physical address of the DRAM chip based on the logical physical address translation table, and performing the operation according to the physical address comprises: receiving a memory write instruction sent by a main body through a cxl.mem protocol, wherein the memory write instruction carries a target logical address for storing data to be written [receive cxl.mem write commands carrying target write addresses and data]; translating the target logical address into a target physical address of the DRAM chip based on a logical physical address comparison table [translates target logical address to physical address via translation table]; and writing the data to be written into a corresponding physical address of the DRAM chip according to the target physical address [writes incoming data to specified physical DRAM].
Claim 6. Malladi et al. discloses the CXL memory module according to claim 2, wherein the CXL memory module further performs memory allocation, and the controller chip is further configured to perform following operations: receiving a request memory instruction sent by a main body through the CXL interface, wherein the request memory instruction carries size information of a memory [host requests memory allocation specifying required capacity/size]; and performing memory allocation according to the size information of the memory, and returning a logical address of a memory allocated for the main body to the main body [controller allocates requested memory range and exposes it as a BAR/base address range to the host].
Claim 7. Malladi et al. discloses the CXL memory module according to claim 6, wherein the controller chip performing the memory allocation according to the size information of the memory, and returning the logical address of the memory allocated for the main body to the main body comprises: allocating a plurality of non-consecutive memory pages to the main body according to the size information of the memory, physical addresses of the plurality of allocated memory pages corresponding to a section of consecutive logical addresses, and returning the logical addresses to the main body [discloses FTL and virtualization engine mapping arbitrary physical blocks/pages into a single continuous logical block address space].
Claim 8. Malladi et al. discloses the CXL memory module according to claim 1, wherein the CXL memory module performs memory allocation, and the controller chip is configured to perform following operations: receiving a request memory instruction through the CXL interface, wherein the request memory instruction carries size information of a memory [receives memory allocation requests carrying memory size requirements over CXL, Fig. 4]]; and perform memory allocation according to the size information of the memory, and return a memory address allocated for a main body to the main body [allocates memory based on requested size and returns allocated base address/BAR to host].
Claim 9. Malladi et al. discloses the CXL memory module according to claim 8, wherein the CXL memory module is shared by a plurality of main bodies [CXL memory module is pooled and shared across multiple servers/host]; and the request memory instruction received by the controller chip further carries a main body identification, and the controller chip returns the memory address allocated for the main body to the main body according to the main body identification [allocation requests specify the initiator/LD-ID, and allocated address ranges are bound/returned to that specific LD-ID/host].
Claim 10. Malladi et al. discloses the CXL memory module according to claim 3, wherein the main body comprises a main CPU, a host, or a computing node [discloses processing circuits, hosts, CPUs, and computing servers].
Claim 11. Malladi et al. discloses the CXL memory module according to claim 3, wherein the main body identification comprises a port number or a source address of the main body [identifies main bodies using host upstream/downstream port bindings or network source addresses (IP/UDP/Ethernet headers)].
Claim 12. Malladi et al. discloses the CXL memory module according to claim 8, wherein the controller chip is further configured to perform following operations: receiving a release memory instruction through the CXL interface, wherein the release memory instruction carries a starting address of a released address block [discloses receiving instructions to unbind, offline, or disable allocated memory blocks starting at designated address ranges]; and performing memory release according to the starting address to release memory data corresponding to the address block [unbinds/de-allocates the specified memory block and releases memory resources].
Claims 13-18 and 20-21 are rejected using the same rationale as claims 1-12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
GIM et al. [US 2025/0335365]; Systems and Methods for Reducing Latency in Memory Tiering. See par. 0057 and 0063.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133
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