DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5, 7-12, 14-17, 19-20, 27 and 32-33 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed: DISPLAY PANEL AND DISPLAY DEVICE HAVING SHIELDING UNIT WITH NOTCH.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0119900 A1) in view of Wang (US 2022/0278183 A1).
As to claim 1, Kim teaches a display panel (Kim, FIG. 3, [0081], “display panel 100”), comprising a pixel driving circuit (Kim, FIG. 8, [0113], “pixel circuit PC”),
wherein the pixel driving circuit (Kim, FIG. 8, [0113], “pixel circuit PC”) comprises a second transistor (Kim, FIG. 8, [0132], “transistor ST3”) and a driving transistor (Kim, FIG. 8, [0128], “transistor ST1 may control a driving current to be applied to the light-emitting element ED”), a first electrode of the second transistor (Kim, FIG. 8, [0132], “transistor ST3”) is connected to a gate of (Kim, see FIG. 8, [0128], at “node N3”) the driving transistor (Kim, FIG. 8, [0128], “transistor ST1”), and a second electrode of the second transistor (Kim, FIG. 8, [0132], “transistor ST3”) is connected to a first electrode of (Kim, see FIG. 8, [0128], at “node N2”) the driving transistor (Kim, FIG. 8, [0128], “transistor ST1”);
wherein the display panel (Kim, FIG. 3, [0081], “display panel 100”) further comprises:
a base substrate (Kim, FIG. 9, [0151], “substrate SUB”);
an active layer (Kim, FIG. 9, [0151], “thin-film transistor (TFT) layer TFTL” comprising “first gate insulating layer GI1” and “third gate insulating layer GI3”), located on a side of the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”), wherein the active layer (Kim, FIG. 9, [0151], “thin-film transistor (TFT) layer TFTL” comprising “first gate insulating layer GI1” and “third gate insulating layer GI3”) comprises:
a second active portion (Kim, FIG. 9, [0148], “semiconductor region ACT3”), configured to form a channel region of the second transistor (Kim, FIG. 9, [0148], “transistor ST3”); and
a third active portion (Kim, FIG. 9, [0145], “semiconductor region ACT1”), wherein the third active portion (Kim, FIG. 9, [0145], “semiconductor region ACT1”) is configured to form a channel region of the driving transistor (Kim, FIG. 8, [0128], “transistor ST1”);
a first metal layer (Kim, FIG. 9, [0153], “metal layer BML1”), located between the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”) and the active layer (Kim, FIG. 9, [0151], “thin-film transistor (TFT) layer TFTL” comprising “first gate insulating layer GI1” and “third gate insulating layer GI3”); and
a second metal layer (Kim, FIG. 9, [0160], “metal layer BML2”), located away from the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”);
wherein orthographic projections of both the first metal layer (Kim, FIG. 9, [0153], “metal layer BML1”) and the second metal layer (Kim, FIG. 9, [0160], “metal layer BML2”) on the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”) at least partially overlap with orthographic projections of (Kim, see FIG. 9) the second active portion (Kim, FIG. 9, [0148], “semiconductor region ACT3”) and the third active portion (Kim, FIG. 9, [0145], “semiconductor region ACT1”) on the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”).
Kim does not teach the third active portion being “connected to the second active portion”; and the second metal layer being “located on a side of the active layer”.
However, Wang teaches the concepts of the third active portion being connected to the second active portion (Wang, see FIGS. 4-5, [0086], the part of “active structure 1101” corresponding to driving transistor T2 is connected to the part of “active structure 1101” corresponding to transistor T5)”; and
the second metal layer being located on a side of the active layer (Wang, see FIGS. 4-5, [0086], “active structure 1101”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “thin-film transistor (TFT) layer TFTL” comprising “first gate insulating layer GI1” and “third gate insulating layer GI3” taught by Kim to be a single layer comprising the “active structure 1101” for active portions of “T2 and T5”, as taught by Wang, in order to provide that, e.g., “the width-to-length ratio of a channel of the switching component T5 is reduced, which reduces the load of the switching component, and reduces a driving current” (Wang, [0088]).
As to claim 14, Kim in view of Wang teaches the display panel according to claim 1, further comprising:
a first electrode layer (Kim, FIG. 7, [0107], a layer of “pixel electrodes of the display device of FIG. 1”), located on the side of the active layer (Wang, see FIGS. 4-5, [0086], “active structure 1101”) away from the base substrate (Kim, see FIG. 9, [0151], “substrate SUB”), wherein the first electrode layer (Kim, FIG. 7, [0107], the layer of “pixel electrodes of the display device of FIG. 1”) comprising a plurality of first electrodes (Kim, FIG. 7, [0104], “first pixel electrodes PE1 and the third pixel electrodes PE3” and “second pixel electrode PE2”), with each of the first electrodes corresponding to one pixel driving circuit (Kim, see FIGS. 5-7);
wherein, the display panel (Kim, FIG. 3, [0081], “display panel 100”) comprises a first sub-pixel (Kim, FIG. 7, [0104], “first pixel electrodes PE1”), a second sub-pixel (Kim, FIG. 7, [0104], “second pixel electrode PE2”) and a third sub-pixel (Kim, FIG. 7, [0104], “third pixel electrodes PE3”), with each sub-pixel corresponding to one pixel driving circuit (Kim, see FIGS. 5-7), wherein a first electrode of the first sub-pixel (Kim, FIG. 7, [0104], “first pixel electrodes PE1”) and a first electrode of the third sub-pixel (Kim, FIG. 7, [0104], “third pixel electrodes PE3”) are located in a first pixel column (Kim, see FIGS. 5-7, [0103], “first data lines DL1 may be electrically connected to first pixel electrodes PE1 and third pixel electrodes PE3”), a first electrode of the second sub-pixel (Kim, FIG. 7, [0104], “second pixel electrode PE2”) is located in a second pixel column (Kim, see FIGS. 5-7, [0103], “second data lines DL2 may be electrically connected to second pixel electrodes PE2”), and the first pixel column (Kim, see FIGS. 5-7, [0103], “first data lines DL1”) and the second pixel column (Kim, see FIGS. 5-7, [0103], “second data lines DL2”) are alternately distributed in a row direction (Kim, see FIGS. 5-7). Examiner renders the same motivation as in claim 1.
As to claim 33, Kim teaches a display device (Kim, FIG. 1, [0055], “display device 10”), comprising the display panel (Kim, FIG. 3, [0062], “display panel 100”) according to claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0119900 A1) in view of Wang (US 2022/0278183 A1) and Wu (CN 115101023 A, hereinafter English translation by Clarivate Analytics).
As to claim 2, Kim teaches the display panel according to claim 1, the second active portion (Kim, FIG. 9, [0148], “semiconductor region ACT3”) comprises:
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a first active sub-portion and a second active sub-portion; and the active layer further comprises: a ninth active portion, connected between the first active sub-portion and the second active sub-portion; wherein the orthographic projection of the first metal layer on the base substrate does not overlap with an orthographic projection of the ninth active portion on the base substrate. Please see above for detailed analysis.
Kim does not teach “the first metal layer is connected to a constant voltage source”.
However, Wu teaches the concept that the first metal layer (Wu, FIGS. 2-3, “shielding metal layer 415”) is connected to a constant voltage source (Wu, FIGS. 2-3, “is electrically connected with the first constant voltage line 11”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “metal layer BML1” taught by Kim to be further connected to “the first constant voltage line 11”, as taught by Wu, in order to provide that “the abnormality turn on the thin film transistor 410 is avoided” (Wu, FIGS. 2-3).
Allowable Subject Matter
Claims 3-5, 7-12, 15-17, 19-20, 27 and 32 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 3, the closest known prior art, i.e., Kim et al. (US 2024/0119900 A1), Wang (US 2022/0278183 A1) and Wu (CN 115101023 A), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the shielding unit comprises: a first shielding portion, arranged corresponding to the second active portion, wherein the first shielding portion has a notch, an orthographic projection of the first shielding portion on the base substrate overlaps with the orthographic projection of the second active portion on the base substrate, and the orthographic projection of the ninth active portion on the base substrate is located within an orthographic projection of the notch on the base substrate; and a second shielding portion, arranged corresponding to the third active portion and connected to the first shielding portion, wherein an orthographic projection of the second shielding portion on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate”.
As to claim 4, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the shielding unit comprises: a second shielding portion, arranged corresponding to the third active portion and connected to a first shielding portion, wherein an orthographic projection of the second shielding portion on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate; the display panel further comprises: a first conductive layer, located on the side of the active layer away from the base substrate, and the first conductive layer comprises: a first conductive block, configured to form the gate of the driving transistor, wherein an orthographic projection of the first conductive block on the base substrate covers the orthographic projection of the third active portion on the base substrate and overlaps with the orthographic projection of the second shielding portion on the base substrate”.
As to claim 5, it depends from claim 4, and is allowable at least for the same reason above.
As to claim 7, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the shielding unit comprises: a first shielding portion, arranged corresponding to the second active portion, wherein the first shielding portion has a notch, an orthographic projection of the first shielding portion on the base substrate overlaps with the orthographic projection of the second active portion on the base substrate, and an orthographic projection of the-a ninth active portion on the base substrate is located within an orthographic projection of the notch on the base substrate; a second shielding portion, arranged corresponding to the third active portion and connected to the first shielding portion, wherein an orthographic projection of the second shielding portion on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate; a first connecting portion, connected to the first shielding portion, wherein an orthographic projection of the first connecting portion on the base substrate extends along a column direction; a second connecting portion, connected to a side, in the column direction, of the second shielding portion away from the first shielding portion, wherein an orthographic projection of the second connecting portion on the base substrate extends along the column direction; a third connecting portion, connected to a side of the second shielding portion in a row direction, wherein an orthographic projection of the third connecting portion on the base substrate extends along the row direction; and a fourth connecting portion, connected to a side, in the row direction, of the second shielding portion away from the third connecting portion, wherein an orthographic projection of the fourth connecting portion on the base substrate extends along the row direction; wherein, in two adjacent shielding units in the row direction, the third connecting portion in one shielding unit is connected to the fourth connecting portion in the other shielding unit; and in two adjacent shielding units in the column direction, the first connecting portion in one shielding unit is connected to the second connecting portion in the other shielding unit”.
As to claims 8-10, they directly or indirectly depend from claim 7, and are allowable at least for the same reason above.
As to claim 11, Kim in view of Wang teaches the display panel according to claim 1, wherein the second active portion (Kim, FIG. 9, [0148], “semiconductor region ACT3”) comprises a first active sub-portion and a second active sub-portion; and
the display panel further comprises:
a first conductive layer (Wang, FIG. 5, [0087], “third metal structure 1103c of the first metal layer 1003”), located on the side of the active layer (Wang, see FIGS. 4-5, [0086], “active structure 1101”) away from the base substrate (Wang, see FIGS. 4-5), wherein the first conductive layer (Wang, FIG. 5, [0087], “third metal structure 1103c of the first metal layer 1003”) comprises:
a gate signal line (Wang, FIGS. 4-5, [0175], “the first metal layer 1003 is a conductive layer, which may include a gate structure of a transistor, or may include a gate signal line”), comprising a main extension portion (Wang, see FIGS. 4-5).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “a secondary extension portion connected to a side of the main extension portion, wherein an orthographic projection of the main extension portion on the base substrate extends along a row direction and covers an orthographic projection of the first active sub-portion on the base substrate, an orthographic projection of the secondary extension portion on the base substrate extends along a column direction and covers an orthographic projection of the second active sub-portion on the base substrate, and the secondary extension portion and a partial structure of the main extension portion are configured to form a gate of the second transistor”; and “the first shielding portion comprises a first shielding sub-portion and a second shielding sub-portion, the first shielding sub-portion corresponds to the first active sub-portion, the second shielding sub-portion corresponds to the second active sub-portion, an orthographic projection of the first shielding sub-portion on the base substrate extends along the row direction and has a fifth width in the column direction, a first overlapping portion is formed between the orthographic projections of the main extension portion and the first shielding sub-portion on the base substrate and has a seventh width in the column direction, and the fifth width is greater than the seventh width; an orthographic projection of the second shielding sub-portion on the base substrate extends along the column direction and has a sixth width in the row direction, a second overlapping portion is formed between the orthographic projections of the secondary extension portion and the second active sub-portion on the base substrate and has an eighth width in the row direction, and the sixth width is greater than the eighth width”.
As to claim 12, it depends from claim 11, and is allowable at least for the reason above.
As to claim 15, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the second metal layer is the first electrode layer”.
As to claims 16-17 and 19, they directly or indirectly depend from claim 15, and are allowable at least for the reason above.
As to claim 20, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the second metal layer is a second source-drain metal layer”.
As to claim 27, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “in a same second repeating unit, structures of a first metal layer, an active layer, a first conductive layer and a second conductive layer in the third pixel driving circuit and structures of a first metal layer, an active layer, a first conductive layer and a second conductive layer in the fourth pixel driving circuit are arranged as mirror images of each other; and in any two adjacent second repeating units in the row direction, structures of a first metal layer, an active layer, a first conductive layer and a second conductive layer in one second repeating unit and structures of a first metal layer, an active layer, a first conductive layer and a second conductive layer in another second repeating unit are arranged as mirror images of each other”.
As to claim 32, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “a second bridge portion, wherein an orthographic projection of the second bridge portion on the base substrate extends along a column direction, one end of the second bridge portion is connected to the fifteenth active portion through a via, and the other end of the second bridge portion is connected to the second initialization signal line through a via, thereby connecting the first electrode of the seventh transistor to the second initialization signal line; and a first connecting line, located in the second display area, wherein an orthographic projection of the first connecting line on the base substrate extends along the column direction, and the first connecting line is connected to two second bridge portions of two adjacent rows”.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure:
Lee et al. (US 2024/0049559 A1) teaches the concept of “metal layers” (e.g., FIG. 4);
Lee et al. (US 2023/0171994 A1) teaches the concept of “metal layer” (e.g., FIG. 16); and
Park et al. (US 2019/0197965 A1) teaches the concept of “bottom shield metal layer … coupled to a voltage source” (Abs.).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Jul. 2, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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