DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 – 4, 14 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 – 4, 12 – 14 and 20 rely on various timing signals, for which a timing generator is necessary. However, a timing generator is first mentioned in claim 19.
Claim 2 recites “to set the second transfer transistor in a conducting state and in a non-conducting state during the first pulse period of the first transfer transistor”. Does the second transfer transistor switch between conducting and non-conducting states? For purposes of art examination, broadest reasonable consideration will be exercised.
Claim 3 recites “to set the second transfer transistor in a conducting state and in a non-conducting state in the in-between period between the first pulse period and the second pulse period and to set the second transfer transistor in a conducting state and in a non-conducting state during the second pulse period of the first transfer transistor”. Does the second transfer transistor switch between conducting and non-conducting states? For purposes of art examination, broadest reasonable consideration will be exercised.
Claim 4 recites “to perform the first and the second series of pulses parallel”. It is not clear what is meant by this limitation. Are the pulses simultaneous? Are there multiple timing generators? For purposes of art examination, broadest reasonable consideration will be exercised.
Claim 14 recites “wherein a conductivity of a controlled section of the first transfer transistor receiving the second voltage value is higher than the conductivity of the controlled section of the first transfer transistor receiving the first voltage value”. It is not clear what is meant by this limitation. For purposes of art examination, broadest reasonable consideration will be exercised.
Claim 20 recites “wherein a conductivity of a controlled section of the first transfer transistor receiving the second voltage value is higher than the conductivity of the controlled section of the first transfer transistor receiving the first voltage value”. It is not clear what is meant by this limitation. For purposes of art examination, broadest reasonable consideration will be exercised.
Claim 20 recites the limitation " the first transfer transistor and the reset transistor" and “the second transfer transistor“. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5 – 6, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 208227176) in view of Huang (US 2013/0206960).
Regarding claim 1, Wang discloses, in at least figure 2, a pixel arrangement, comprising: a photodiode (PD), a first and a second circuit node (see fig. 2), a first transfer transistor (TX_HCG) coupled to the photodiode and to the first circuit node (FD), a second transfer transistor (TX_LCG) coupled to the photodiode and to the second circuit node, an amplifier (SF) with an input coupled to the first circuit node, a supply terminal (VDD), a first DCG), and a reset transistor (RST), wherein the first coupling transistor,
In the same field of endeavor, Huang teaches a pixel circuit and image sensor that includes multiple conversion gain transistors (fig. 5-8; ¶56-60). In light of the teaching of Huang, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to use Huang’s configuration in Wang’s system because an artisan of ordinarily skill would recognize that this would result in increase of dynamic range in bright scenes and achieve high sensitivity in darker scenes.
Regarding claim 5, Wang in view of Huang disclose the limitations of claim 1. Wang also teaches wherein the pixel arrangement comprises a gain capacitor which is coupled to a node between the first coupling transistor and the second coupling transistor (figs. 1, 2, 4, 5).
Regarding claim 6, Wang in view of Huang disclose the limitations of claim 1. The combination also teaches wherein the first and the second transfer transistor are realized as field-effect transistors (see rejection of claim 1). The combination fails to explicitly disclose wherein the first transfer transistor has a first threshold voltage and the second transfer transistor has a second threshold voltage, and wherein the first threshold voltage is different from the second threshold voltage. It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to adjust the threshold of the each transistor to a particular value, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 19, Wang in view of Huang disclose the limitations of claim 1. Wang also teaches timing generator configured to provide a first transfer signal to a control terminal of the first transfer transistor, a second transfer signal to a control terminal of the second transfer transistor, a first coupling signal to a control terminal of the first coupling transistor, a second coupling signal to a control terminal of the second coupling transistor and a reset signal to a control terminal of the reset transistor (see rejection of claim 1).
Claim(s) 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 208227176) in view of Huang (US 2013/0206960) in view of Innocent (US 2022/0264038).
Regarding claim 2, Wang in view of Huang disclose the limitations of claim 1. The combination fails to explicitly disclose wherein in an exposure phase the pixel arrangement is configured to set the first transfer transistor and the reset transistor in a conducting state for a first pulse period and to set the second transfer transistor in a conducting state and in a non-conducting state during the first pulse period of the first transfer transistor.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the invention of Wang/Huang with the teachings of Innocent. Wang/Huang discloses pixel arrangements with first and second transfer transistors and a reset transistor. Innocent teaches pulsed exposures (figs. 4-5, 8; ¶37-57). One of ordinary skill in the art would have recognized that applying the known technique of using pulsed exposures, as taught by Innocent, with the invention of Wang/Huang would have yielded predictable results and resulted in an improved system with controlled charge overflow.
Regarding claim 3, Wang in view of Huang in view of Innocent disclose the limitations of claim 2. Innocent also teaches (as far as can be understood) wherein in the exposure phase the pixel arrangement is configured to set the first transfer transistor in a conducting state for a second pulse period and in a non- conducting state during an in-between period between the first pulse period and the second pulse period, to set the reset transistor in a conducting state during the second pulse period and during the in-between period between the first pulse period and the second pulse period, to set the second transfer transistor in a conducting state and in a non-conducting state in the in-between period between the first pulse period and the second pulse period and to set the second transfer transistor in a conducting state and in a non-conducting state during the second pulse period of the first transfer transistor (figs. 4-5, 8; ¶37-57).
Regarding claim 4, Wang in view of Huang in view of Innocent disclose the limitations of claim 1. Innocent also teaches (as far as can be understood) wherein the pixel arrangement is configured to set the first transfer transistor in a conducting state during pulses of a first series of pulses and to set the first transfer transistor in a non-conducting state during in-between periods between pulses of the first series of pulses, to set the reset transistor in a conducting state during the pulses of the first series of pulses and during the in-between periods between the pulses of the first series of pulses, to set the second transfer transistor in a conducting state during pulses of a second series of pulses and in a non-conducting state during in-between periods between the pulses of the second series of pulses, and to perform the first and the second series of pulses parallel, and wherein a first frequency of the first series of pulses is lower than a second frequency of the second series of pulses (figs. 4-5, 8; ¶37-57).
Claim 20 is rejected as applied to claim 2 above. The method steps as claimed would have been implied by the apparatus of Wang in view of Huang in view of Innocent.
Claim(s) 7 – 11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 208227176) in view of Huang (US 2013/0206960) in view of Meynants (US 2021/0235027).
Regarding claim 7, Wang in view of Huang disclose the limitations of claim 1. The combination fails to explicitly disclose wherein the pixel arrangement comprises a further reset transistor which couples an output of the amplifier to a reference potential terminal.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the invention of Wang/Huang with the teachings of Innocent. Wang/Huang discloses pixel arrangements with first and second transfer transistors and a reset transistor. Meynants teaches a pixel arrangement with second first, second and reset transistors coupled to an output of the amplifier and a reference potential terminal (figs. 3; ¶113). One of ordinary skill in the art would have recognized that applying the known technique of addition transistors, as taught by Meynants, with the invention of Wang/Huang would have yielded predictable results and resulted in an improved system with adjustable conversion gain.
Regarding claim 8, Wang in view of Huang disclose the limitations of claim 1. The combination fails to explicitly disclose wherein the pixel arrangement comprises a first capacitor and a first transistor, and wherein the first transistor couples an output of the amplifier to the first capacitor.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the invention of Wang/Huang with the teachings of Innocent. Wang/Huang discloses pixel arrangements with first transistors and a capacitor and an amplifier. Meynants teaches a pixel arrangement with first capacitor and first transistor coupling the output of the amplifier to the capacitor (figs. 3; ¶113). One of ordinary skill in the art would have recognized that applying the known technique of addition transistors, as taught by Meynants, with the invention of Wang/Huang would have yielded predictable results and resulted in an improved system with adjustable conversion gain.
Regarding claim 9, Wang in view of Huang in view of Meynants disclose the limitations of claim 8. Meynants also teaches wherein the pixel arrangement comprises a second capacitor and a second transistor, and wherein the second transistor couples the first capacitor to the second capacitor (figs. 3; ¶113).
Regarding claim 10, Wang in view of Huang in view of Meynants disclose the limitations of claim 9. Meynants also teaches wherein the pixel arrangement comprises a third transistor and an output amplifier, and wherein the third transistor couples the second capacitor to an input of the output amplifier (figs. 3; ¶113).
Regarding claim 11, Wang in view of Huang in view of Meynants disclose the limitations of claim 10. Meynants also teaches wherein the pixel arrangement comprises a third capacitor coupled to a node between the third transistor and the input of the output amplifier (figs. 3; ¶113).
Regarding claim 16, Wang in view of Huang in view of Meynants disclose the limitations of claim 9. Meynants also teaches wherein the pixel arrangement comprises a further first capacitor and a further first transistor, and wherein the further first transistor couples the output of the amplifier to the further first capacitor (figs. 3; ¶113).
Regarding claim 17, Wang in view of Huang in view of Meynants disclose the limitations of claim 9. Meynants also teaches wherein the pixel arrangement comprises a further second capacitor and a further second transistor, and wherein the further second transistor couples the further first capacitor to the further second capacitor, wherein the pixel arrangement comprises a further output amplifier with an input coupled to the further second transistor, and wherein the further second capacitor is coupled to a node between the further second transistor and the input of the further output amplifier (figs. 3; ¶113).
Claim(s) 12 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 208227176) in view of Huang (US 2013/0206960) in view of Meynants in view of Innocent.
Regarding claim 12, Wang in view of Huang in view of Meynants disclose the limitations of claim 11. The combination fails to explicitly disclose wherein the pixel arrangement is configured to store an output voltage of the amplifier in the third capacitor during a first storage phase, in the second capacitor during a second storage phase and in the first capacitor during a third storage phase.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the invention of Wang/Huang with the teachings of Innocent. Wang/Huang discloses pixel arrangements with first and second transfer transistors and a reset transistor. Innocent teaches pulsed exposures and plural storage states (figs. 4-5, 8; ¶37-57). One of ordinary skill in the art would have recognized that applying the known technique of using pulsed exposures, as taught by Innocent, with the invention of Wang/Huang would have yielded predictable results and resulted in an improved system with controlled charge overflow.
Regarding claim 13, Wang in view of Huang in view of Innocent disclose the limitations of claim 12. Innocent also teaches (as far as can be understood) wherein the pixel arrangement is configured to set the first coupling transistor and the second coupling transistor in a conducting state during the first and the second storage phase (figs. 4-5, 8; ¶37-57).
Regarding claim 14, Wang in view of Huang in view of Innocent disclose the limitations of claim 12. Innocent also teaches (as far as can be understood) is configured to set the second transfer transistor in a conducting state by a first voltage value before the first storage phase, to set the first transfer transistor in a conducting state by the first voltage value between the first storage phase and the second storage phase and to set the first transfer transistor in a conducting state by a second voltage value between the second storage phase and the third storage phase and wherein a conductivity of a controlled section of the first transfer transistor receiving the second voltage value is higher than the conductivity of the controlled section of the first transfer transistor receiving the first voltage value (figs. 4-5, 8; ¶37-57).
Claim(s) 21 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 208227176) in view of Huang (US 2013/0206960) in view of Meynant2 (US 2009/0256060).
Regarding claim 21, Wang discloses, in at least figure 2, a pixel arrangement, comprising: a photodiode (PD), a first and a second circuit node (see fig. 2), a first transfer transistor (TX_HCG) coupled to the photodiode and to the first circuit node (FD), a second transfer transistor (TX_LCG) coupled to the photodiode and to the second circuit node, an amplifier (SF) with an input coupled to the first circuit node, a supply terminal (VDD), a first DCG), and a reset transistor (RST), wherein the first coupling transistor,
In the same field of endeavor, Huang teaches a pixel circuit and image sensor that includes multiple conversion gain transistors (fig. 5-8; ¶56-60). In light of the teaching of Huang, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to use Huang’s configuration in Wang’s system because an artisan of ordinarily skill would recognize that this would result in increase of dynamic range in bright scenes and achieve high sensitivity in darker scenes. The combination fails to explicitly disclose three sample-and-hold capacitors.
In the same field of endeavor, Meynants2 teaches a pixel circuit and image sensor that includes multiple sample and hold circuits with capacitors (fig. 6-9). In light of the teaching of Meynants2, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to use Meynants2’ configuration in Wang’s system because an artisan of ordinarily skill would recognize that this would result in reduced noise and reduced size.
Regarding claim 22, Wang in view of Huang in view of Meynants2 disclose the limitations of claim 21. Meynants2 also teaches (as far as can be understood) is wherein the three sample-and-hold capacitors comprise a first capacitor, a second capacitor, and a third capacitor or a further first capacitor (figs. 6-9).
Contact
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/ANTOINETTE T SPINKS/Primary Examiner, Art Unit 2639
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