DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8, 9 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park U.S. Patent Publication No. 2017/0186363 (hereinafter Park) in view of Xie et al. U.S. Patent Publication No. 2025/0273134 (hereinafter Xie).
Consider claim 1, Park teaches a shift register comprising: a cascade output sub-circuit, an output control sub-circuit, and a scan output sub-circuit (Figure 3, 340); the cascade output sub-circuit is electrically connected to an input terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a second power supply terminal, a cascade output terminal, a first node, a second node, and a third node respectively (Figure 3, 341-343, CRY[n-1], CLK1, GLK2, VGH, VGL, CRY[n], Q2, Q1, M2-M3 node), and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascade output terminal under control of signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node (Figure 3, CRY[n] under control of CLK1, GLK2, CRY[n-1], Q2, Q1, M2-M3 node); the output control sub-circuit is electrically connected to a first control signal terminal, a second control signal terminal and a third control signal terminal, the first node, the second node, the third node, a fourth node, and a fifth node respectively (Figure 3, 344, OEB, OE, VGL, VGH, Q2, Q4, Q1, Q3 and M2-M3 node) and is configured to provide a signal of the first node to the fourth node and to provide a signal of the second node to the fifth node under control of signals of the first node, the third node, and the first control signal terminal to the third control signal terminal (Figure 3, Q2-Q4 and Q1-Q3 under control under control OEB, OE, VGL, VGH, Q2, Q1, and M2-M3 node); and the scan output sub-circuit is electrically connected to the fourth node, the fifth node, a scan signal output terminal, the first power supply terminal, and a power supply terminal, respectively (Figure 3, Q4, Q3, GI[n], VGH and GLK2), and is configured to output the signal of the first power supply terminal or a power supply terminal to the scan signal output terminal under control of signals of the fourth node and the fifth node (Figure 3, GI[n] under control of Q3-Q4).
Park does not appear to specifically disclose output sub-circuit is electrically connected to second power supply.
However, in a related field of endeavor, Xie teaches shift registers in figure 1 and further teaches output sub-circuit is electrically connected to second power supply (Figure 27, M29-M30 and VGL).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide VGL for the output circuit as taught by Xie in order to cause the output signal SOUT to become low potential when low potential of the second potential signal VGL is transmitted through the transistor M30 as suggested in [0205].
Consider claim 8, Park and Xie teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein the scan output sub-circuit comprises a seventh transistor, and an eighth transistor; a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the scan signal output terminal; and a control electrode of the eighth transistor is electrically connected to the fifth node, a first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second power supply terminal.
However, Xie teaches wherein the scan output sub-circuit comprises a seventh transistor, and an eighth transistor; a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the scan signal output terminal (Figure 27, M29 and respective connections); and a control electrode of the eighth transistor is electrically connected to the fifth node, a first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second power supply terminal (Figure 27, M30 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide M29-M30, VGH and VGL as taught by Xie in order to cause the output signal SOUT to become low potential or high potential as suggested in [0204-0205].
Consider claim 9, Park and Xie teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein the scan output sub-circuit further comprises: a second capacitor comprising a first plate and a second plate; the first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.
However, Xie teaches wherein the scan output sub-circuit further comprises: a second capacitor comprising a first plate and a second plate (Figure 27, C7); the first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal (Figure 27, C7 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide C7 with the benefit that due to the storage effect of the capacitor C7, the node N6 maintains the high potential from the previous phase as suggested in [0201].
Consider claim 13, Park and Xie teach all the limitations of claim 1. In addition, Park teaches a cascade output terminal of an i-th stage of shift register is electrically connected to a input terminal of an (i+1)-th stage of shift register (Figure 2, blocks 1-3, and CRY[1]-[2], where first block receives FLM), 1<=i <= M-1, and M is a total number of stages of the shift registers (Figure 2, SRC1-SCRC3).
Consider claim 14, Park and Xie teach all the limitations of claim 1. In addition, Park teaches a method for driving a shift register, configured to drive the shift register according to claim 1,wherein the method comprises: providing, by the cascade output sub-circuit, a signal of the first power supply terminal or the second power supply terminal to the cascade output terminal under control of signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node and the third node (Figure 3, CRY[n] under control of CLK1, GLK2, CRY[n-1], Q2, Q1, M2-M3 node); providing, by the output control sub-circuit, a signal of the first node to the fourth node and a signal of the second node to the fifth node under control of signals of the first node, the third node and the first control signal terminal to the third control signal terminal (Figure 3, Q2-Q4 and Q1-Q3 under control under control OEB, OE, VGL, VGH, Q2, Q1, and M2-M3 node); and outputting, by the scan output sub-circuit, a signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under control of signals of the fourth node and the fifth node (Figure 3, GI[n] under control of Q3-Q4).
Allowable Subject Matter
Claims 2-7, 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to specifically disclose the details of the output control sub-circuit, the ninth-twenty fifth transistors, capacitors and/or the working processes mentioned in claim 2, 10-12 in combination to other limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO W FLORES whose telephone number is (571)272-5512. The examiner can normally be reached Monday-Friday, 7am-4pm, EST.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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