DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are currently pending and prosecuted.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 July 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 2 objected to because of the following informalities: there is a period following the “third driving transistor” limitation rather than a “;” and an “and”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al., US PG-Pub 2023/0071229, hereinafter Lee.
Regarding Claim 1, Lee teaches a touch circuit for stably maintaining an output voltage level using transistors (Fig. 13, and corresponding descriptions; [0073]), the touch circuit comprising:
a first driving transistor (T1) (first transistor T1) having a drain electrode and a gate electrode connected to an input power supply (VDD) (first driving voltage ELVDD; Fig. 13, and corresponding descriptions), and having a source electrode connected to a drain electrode of a second driving transistor (T2) (second transistor T2; Fig. 13, and corresponding descriptions); and
the second driving transistor (T2) having a gate electrode connected to one electrode of a capacitor (capacitor Cst; Fig. 13, and corresponding descriptions), and having the drain electrode connected to the source electrode of the first driving transistor (T1) (Fig. 13, and corresponding descriptions), and having a source electrode connected to ground (Fig. 13, and corresponding descriptions), the capacitor having another electrode connected to the input power supply (VDD) (Fig. 13, and corresponding descriptions).
Regarding Claim 3, Lee teaches the touch circuit of claim 1, further comprising:
a fifth driving transistor (T5) (sixth transistor T6; Fig. 13, and corresponding descriptions) having a gate electrode connected to the drain electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a source electrode connected to the gate electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a drain electrode connected to the input power supply (VDD) (Fig. 13, and corresponding descriptions).
Regarding Claim 4, Lee teaches the touch circuit of claim 3, wherein the first driving transistor (T1) to the fourth driving transistor (T4) are N-type MOSFETs ([0149]), and the fifth driving transistor (T5) is a P-type MOSFET ([0149]).
Regarding Claim 5, Lee teaches the touch circuit of claim 1, further comprising:
a sixth driving transistor (T6) (third transistor T3; Fig. 13, and corresponding descriptions) having a drain electrode connected to the gate electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a gate electrode connected to the drain electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a source electrode connected to the ground (Fig. 13, and corresponding descriptions).
Regarding Claim 2, Lee teaches a touch circuit for stably maintaining an output voltage level using transistors (Fig. 13, and corresponding descriptions; [0073]), the touch circuit comprising:
a first driving transistor (T1) (first transistor T1 having a drain electrode and a gate electrode connected to a source electrode of a third driving transistor (T3) (fifth transistor T5; Fig. 13, and corresponding descriptions), and having a source electrode connected to a drain electrode of a second driving transistor (T2) (second transistor T2; Fig. 13, and corresponding descriptions);
the second driving transistor (T2) having a gate electrode connected to one electrode of a capacitor (capacitor Cst; Fig. 13, and corresponding descriptions), and having the drain electrode connected to the source electrode of the first driving transistor (T1) (Fig. 13, and corresponding descriptions), and having a source electrode connected to ground (Fig. 13, and corresponding descriptions), the capacitor having another electrode connected to an input power supply (VDD) (first driving voltage ELVDD; Fig. 13, and corresponding descriptions);
the third driving transistor (T3) having a drain electrode and a gate electrode connected to the input power supply (VDD) (Fig. 13, and corresponding descriptions), and having the source electrode connected to the drain electrode of the first driving transistor (T1) (Fig. 13, and corresponding descriptions); and connected to a drain electrode of a fourth driving transistor (T4) (fourth transistor T4; Fig. 13, and corresponding descriptions) [; and]
the fourth driving transistor (T4) having a gate electrode connected to the gate electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a drain electrode connected to the drain electrode of the first driving transistor (T1) (Fig. 13, and corresponding descriptions), and having a source electrode connected to the ground (Fig. 13, and corresponding descriptions).
Regarding Claim 7, Lee teaches the touch circuit of claim 2, further comprising:
a fifth driving transistor (T5) (sixth transistor T6; Fig. 13, and corresponding descriptions) having a gate electrode connected to the drain electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a source electrode connected to the gate electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a drain electrode connected to the input power supply (VDD) (Fig. 13, and corresponding descriptions).
Regarding Claim 8, Lee teaches the touch circuit of claim 7, wherein the first driving transistor (T1) to the fourth driving transistor (T4) are N-type MOSFETs ([0149]), and the fifth driving transistor (T5) is a P-type MOSFET ([0149]).
Regarding Claim 9, Lee teaches the touch circuit of claim 2, further comprising:
a sixth driving transistor (T6) (third transistor T3; Fig. 13, and corresponding descriptions) having a drain electrode connected to the gate electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a gate electrode connected to the drain electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions), and having a source electrode connected to the ground (Fig. 13, and corresponding descriptions).
Regarding Claim 6, Lee teaches a touch sensing device for stably maintaining an output voltage level using transistors (Fig. 13, and corresponding descriptions; [0073]), the touch sensing device comprising:
a first driving transistor (T1) (first transistor T1) having a drain electrode and a gate electrode connected to an input power supply (VDD) (first driving voltage ELVDD; Fig. 13, and corresponding descriptions), and having a source electrode connected to a drain electrode of a second driving transistor (T2) (second transistor T2; Fig. 13, and corresponding descriptions);
the second driving transistor (T2) having a gate electrode connected to one electrode of a capacitor (capacitor Cst; Fig. 13, and corresponding descriptions), and having the drain electrode connected to the source electrode of the first driving transistor (T1) (Fig. 13, and corresponding descriptions), and having a source electrode connected to ground (Fig. 13, and corresponding descriptions), the capacitor having another electrode connected to the input power supply (VDD) (Fig. 13, and corresponding descriptions);
a touch electrode connected to the gate electrode of the second driving transistor (T2) ([0073], [0080], [0150]-[0154]); and
an output stage connected to the drain electrode of the second driving transistor (T2) (Fig. 13, and corresponding descriptions),
wherein when the touch electrode is not touched, a voltage of the output stage becomes a voltage close to the ground ([0073], [0080], [0150]-[0154]), or when the touch electrode is touched, the voltage of the output stage becomes a voltage close to the input power supply (VDD) ([0073], [0080], [0150]-[0154]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN T REED whose telephone number is (571)272-7234. The examiner can normally be reached M-F: 0800-1800.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
STEPHEN T. REED
Primary Examiner
Art Unit 2627
/Stephen T. Reed/Primary Examiner, Art Unit 2627
Prosecution Insights