Prosecution Insights
Last updated: October 27, 2026
Application No. 19/150,323

MODULE LEVEL POWER ELECTRONICS, DIAGNOSIS MANAGEMENT SYSTEM, AND DIAGNOSIS MANAGEMENT METHOD

Non-Final OA §102§103
Filed
Jul 23, 2025
Priority
Jul 12, 2023 — RE 10-2023-0090458 +1 more
Examiner
ORTIZ, ELIM
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hanwha Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
479 granted / 603 resolved
+11.4% vs TC avg
Strong +23% interview lift
Without
With
+22.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
15 currently pending
Career history
629
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
62.6%
+22.6% vs TC avg
§102
16.4%
-23.6% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 603 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, 4, 7-9 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2024/0405561) Regarding claim 1 Yu teaches a module-level power electronics (MLPE) (see para 0007), comprising: a processor configured to execute a self-validation mode (see para 0009) on the basis of a self-validation request signal received during operation or stop of an inverter connected to the MLPE (see para 0012), detect, in the self-validation mode, whether there is an installation fault between a photovoltaic module and the MLPE (see para 00016-0018) or a component fault within the MLPE (see 0020), and transmit, to a validation management system, validation result information regarding whether or not the installation fault and the component fault are detected (see 0012). Regarding claim 15, Yu teaches a validation management method performed by a module-level power electronics (MLPE) device, comprising: executing a self-validation mode on the basis of a self-validation request signal received during operation or stop of an inverter connected to the MLPE, detecting, in the self-validation mode, whether there is an installation fault between the photovoltaic module and the MLPE or a component fault within the MLPE; and transmitting, to a validation management system, validation result information regarding whether or not the installation fault and the component fault are detected (see the rejection of claim 1). Regarding claim 3 Yu teaches, wherein the processor is further configured to detect the installation fault on the basis of first fault information indicating at least one of overvoltage of the photovoltaic module, overcurrent of the photovoltaic module, overvoltage of the MLPE device, overcurrent of the MLPE, or overheating of the MLPE (see para 0081 and 0089). Regarding claim 4 Yu teaches, wherein the processor is further configured to receive measurement information obtained by measuring at least one of an output voltage of the photovoltaic module, an output current of the photovoltaic module, an output voltage of the MLPE device, an output current of the MLPE, or a temperature of the MLPE, and detect, based on the measurement information, whether there is the installation fault due to at least one of overvoltage, overcurrent, or overheating (see para 0081 and 0089). Regarding claim 7 Yu teaches, wherein the processor is further configured to operate the MLPE again in the normal mode based on the number of detections not exceeding the preset number of times (see para 0081 and 0089). Regarding claim 16 Yu teaches, wherein the executing comprises receiving the self-validation request signal from the validation management system based on a user input requesting self- validation (see para 0055). Regarding claim 17 Yu teaches, wherein the detecting comprises detecting the installation fault on the basis of first fault information indicating at least one of overvoltage of the photovoltaic module, overcurrent of the photovoltaic module, overvoltage of the MLPE device, overcurrent of the MLPE, or overheating of the MLPE (see para 0055). Regarding claim 18 Yu teaches, wherein the detecting comprises detecting the component fault on the basis of second fault information indicating at least one of a rapid shutdown (RSD) operation fault, a voltage sensor fault of the MLPE, a gate driver fault of the MLPE, a power supply fault of the processor, or an analog-to-digital converter fault (see para 0055). Regarding claim 19 Yu teaches, , further comprising: detecting the installation fault between the photovoltaic module and the MLPE or the component fault within the MLPE device while the MLPE is operating in a normal mode; stopping operation of the MLPE based on the installation fault or the component fault; and executing the self-validation mode based on the number of detections of the installation fault or component fault exceeding a preset number of times (see para 0055). Regarding claim 20 Yu teaches, further comprising: detecting the component fault within the MLPE while the MLPE is operating in the normal mode, and executing the self-validation mode based on a fault condition duration corresponding to the component fault exceeding a preset time (see para 0055). Claims 10-12 and 14 are rejected under 35 U.S.C. 102(a) as being anticipated by Mostmans (WO 2015116002). Regarding claim 10 Marcus a validation management system communicating with a module- level power electronics (see para 0003) (MLPE) device, the validation management system comprising: a processor configured to transmit a self-validation request signal (see 0009) to the MLPE based on receiving a user input requesting self-validation, receive validation result information regarding an installation fault between a photovoltaic module and the MLPE (see para 0018) or a component fault within the MLPE in response to the self- validation request signal, and perform a preset response operation on the basis of the validation result information (see para 0018). Regarding claim 11 Marcus teaches, wherein the processor is further configured to display, on a display, the validation result information including information on occurrence of an installation fault or component fault, information regarding a cause of a fault, or information regarding a solution to a fault (see para 0055). Regarding claim 12 Marcus teaches, wherein the preset response operation includes an operation of displaying information on the occurrence of the installation fault or component fault on the display, an operation of transmitting a self-validation re-request signal to the MLPE, an operation of executing a service call for inspection of the MLPE device, or an operation of transmitting a normal mode operation signal to the MLPE (see para 0055). Regarding claim 14 Marcus teaches, wherein the processor is further configured to transmit a normal mode operation signal to the MLPE based on receiving a user input requesting operation in a normal mode according to the validation result information (see para 0081 and 0089; Yu). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 5, 6, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Choi (KR 20170056763). Regarding claim 2 Yu teaches the MLPR of claim 1. Yet does not disclose wherein the processor is further configured to receive the self-validation request signal from the validation management system based on a user input requesting self- validation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YU with the teachings of Choi having the processor is further configured to receive the self-validation request signal from the validation management system based on a user input requesting self- validation in order to provide advance safety and hazard mitigation. Regarding claim 5 Yu teaches the MLPR of claim 1. Yet does not disclose the processor is further configured to detect the component fault on the basis of second fault information indicating at least one of a rapid shutdown (RSD) operation fault, a voltage sensor fault of the MLPE, a current sensor fault of the MLPE, a gate driver fault of the MLPE, a power supply fault of the MLPE, or an analog-to-digital converter fault of the MLPE (see para 0038, Choi). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YU with the teachings of Choi having the processor is further configured to detect the installation fault between the photovoltaic module and the MLPE or the component fault within the MLPE while the MLPE is operating in a normal mode, stop operation of the MLPE based on the installation fault or the component fault, and execute the self-validation mode based on the number of detections of the installation fault or component fault exceeding a preset number of times in order to provide advance safety and hazard mitigation Regarding claim 6 Yu teaches the MLPR of claim 1. Yet does not disclose the processor is further configured to detect the installation fault between the photovoltaic module and the MLPE or the component fault within the MLPE while the MLPE is operating in a normal mode, stop operation of the MLPE based on the installation fault or the component fault, and execute the self-validation mode based on the number of detections of the installation fault or component fault exceeding a preset number of times (see para 0038, Choi). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YU with the teachings of Choi having the processor is further configured to detect the installation fault between the photovoltaic module and the MLPE or the component fault within the MLPE while the MLPE is operating in a normal mode, stop operation of the MLPE based on the installation fault or the component fault, and execute the self-validation mode based on the number of detections of the installation fault or component fault exceeding a preset number of times in order to provide advance safety and hazard mitigation. Regarding claim 8 Yu teaches the MLPR of claim 1. Yet does not disclose wherein the processor is further configured to detect the component fault within the MLPE while the MLPE is operating in a normal mode and executes the self-validation mode based on a fault condition duration corresponding to the component fault exceeding a preset time. However, Choi in the same field teaches the processor is further configured to detect the component fault within the MLPE while the MLPE is operating in a normal mode and executes the self-validation mode based on a fault condition duration corresponding to the component fault exceeding a preset time (para 0012-0015; D3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu with the teachings of Choi having the processor is further configured to detect the component fault within the MLPE while the MLPE is operating in a normal mode and executes the self-validation mode based on a fault condition duration corresponding to the component fault exceeding a preset time in order to provide advance safety and hazard mitigation. Regarding claim 9 Yu teaches the MLPR of claim 1. Yet does not disclose wherein the validation result information includes information on occurrence of the detected installation fault or component fault, information regarding a cause of the installation fault or component fault, and information regarding a solution to the installation fault or component fault. However, Choi in the same field teaches the validation result information includes information on occurrence of the detected installation fault or component fault, information regarding a cause of the installation fault or component fault, and information regarding a solution to the installation fault or component fault (para 0012-0015; D3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu with the teachings of Choi having the validation result information includes information on occurrence of the detected installation fault or component fault, information regarding a cause of the installation fault or component fault, and information regarding a solution to the installation fault or component fault in order to provide advance safety and hazard mitigation. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Marcus (WO 2015116002) in view of Choi (KR 20170056763) Regarding claim 13 Marcus teaches the validation management system of claim 12. Yet does not disclose wherein the processor is further configured to transmit a self-validation re-request signal for the self-validation to the MLPE based on receiving a user input requesting the self-validation again according to the validation result information. However, Choi in the same field teaches the processor is further configured to transmit a self-validation re-request signal for the self-validation to the MLPE based on receiving a user input requesting the self-validation again according to the validation result information (That is, the monitoring module 300 receives data in a binary form from the micro-inverter 200. In order to convert the binary data into web-based data so that the data can be recognized by the operation server 400 or the like, The transmission / reception unit 320 performs data processing on the monitoring information.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Marcus with the teachings of Choi having the processor is further configured to transmit a self-validation re-request signal for the self-validation to the MLPE based on receiving a user input requesting the self-validation again according to the validation result information in order to operational and safety benefits. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIM ORTIZ whose telephone number is (571)270-7114. The examiner can normally be reached 9:30am-6:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at (571) 272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIM ORTIZ/Primary Examiner, Art Unit 2836
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Prosecution Timeline

Jul 23, 2025
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.8%)
2y 9m (~1y 6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 603 resolved cases by this examiner. Grant probability derived from career allowance rate.

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