Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al 2022/0230593 hereinafter, Huang in view of Wang 2018/0082629 hereinafter, Wang.
In regards to claim 1, Huang teaches (Original) a shift register, comprising:
an input sub-circuit configured to transmit a signal at an input terminal to a first
node in response to a first level signal at a first clock signal terminal;(fig. 8 (3 to Q3) VHG Ck1)
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a first output sub-circuit configured to transmit a first level signal at a first level
signal terminal to an output terminal in response to a first level signal at the first node (fig. 8 (4));
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a first control sub-circuit configured to transmit a second level signal at a
second level signal terminal to a second node in response to a first level signal at the
input terminal (fig. 8 (T1))Q1);
Huang fails to teach a second control sub-circuit configured to transmit a first level signal at the first level signal terminal to a third node in response to a first level signal at the first clock signal terminal, and transmit a second level signal at the second level signal terminal to the third node in response to a first level signal at the second clock signal terminal;
However, Wang teaches a second control sub-circuit configured to transmit a first level signal at the first level signal terminal to a third node in response to a first level signal at the first clock signal terminal (fig. 12 (Clk’), and transmit a second level signal at the second level signal terminal to the third node in response to a first level signal at the second clock signal terminal (fig. 12 (CLKb) Pu) and wherein the first control sub-circuit is connected to a second level (fig. 12 Vss).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Huang to further include a second control sub-circuit configured to transmit a first level signal at the first level signal terminal to a third node in response to a first level signal at the first clock signal terminal, and transmit a second level signal at the second level signal terminal to the third node in response to a first level signal at the second clock signal terminal as taught by Wang in order to maintain stability [0068].
Therefore, Huang in view of Wang teaches a storage sub-circuit configured to store a voltage between the second node and the third node (fig. 12 (C1/C2) Wang; and
a second output sub-circuit (fig. 8 T4, T1, T6) Huang configured to electrically connect the second level signal terminal (fig. 8 VGL) Huang with the output terminal in response to a second level signal at the first node and a first level signal at the second node (fig. 8 (Q3)) Huang, and maintain an on/off state between the second level signal terminal and the output terminal in response to a second level signal at the first node and a second level signal at the second node [154-156] Huang and (fig. 12 MC1 and Vss) Wang.
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In regards to claim 2, Huang in view of Wang teaches (Original) the shift register of claim 1, wherein the first control sub-circuit comprises: a second transistor (fig. 8 T1) Huang, wherein a control electrode of the second transistor is electrically connected to the input terminal (fig. 8 gate of T1 to input) Huang, a first electrode of the second transistor is electrically connected to the second level signal terminal, and a second electrode of the second transistor is electrically connected to the second node (fig. 8 VGH and fig. 8 Q1) Huang and (fig. 12 Vss) Wang.
In regards to claim 3, Huang in view of Wang teaches shift register of claim 1, wherein the second control sub-circuit comprises: a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first clock signal terminal, a first electrode of the fifth transistor is electrically connected to the first level signal terminal, and a second electrode of the fifth transistor is electrically connected to the third node; and a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the second clock signal terminal, a first electrode of the sixth transistor is electrically connected to the second level signal terminal, and a second electrode of the sixth transistor is electrically connected to the third node.(fig. 12 (MC2 and MC3 CLk’ and CLKB) Wang in view of (fig. 8 Q3/Q2) Huang
In regards to claim 4, Huang in view of Wang teaches shift register of claim 1, wherein the storage sub-circuit comprises:a first capacitor, wherein two terminals of the first capacitor are electrically connected to the third node and the second node, respectively (fig. 12 C1/C2) Wang in view of fig. 8 C1 Huang)
In regards to claim 5, Huang in view of Wang teaches shift register of any one of claims to 4, wherein the input sub-circuit comprises: a first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the input terminal, and a second electrode of the first transistor is electrically connected to the first node (fig. 8 (T3 input and Q2)) Huang.
In regards to claim 6, Huang in view of Wang teaches shift register of, wherein the first output sub-circuit comprises: an eighth transistor (fig. 8 (T5)) Huang, wherein a control electrode of the eighth transistor is electrically connected to the first node (fig. 8 (Q2) Huang), a first electrode of the eighth transistor is electrically connected to the first level signal terminal, and a second electrode of the eighth transistor is electrically connected to the output terminal; and a second capacitor, wherein two terminals of the second capacitor are electrically connected to the output terminal and the first node, respectively.(fig. 12 (T5 and C3) Huang
In regards to claim 7, Huang in view of Wang teaches shift register of any one of claims 1-to 4, wherein the second output sub-circuit comprises: a first control unit configured to transmit a first level signal at the first level signal terminal or a signal at the first clock signal terminal to a fourth node in response to a first level signal at the second node (fig. 8 CK1 to Q1) Huang); a second control unit configured to transmit a second level signal at the second level signal terminal to the fourth node in response to a first level signal at the first node; and an output unit configured to transmit a second level signal at the second level signal terminal to the output terminal in response to a first level signal at the fourth node. (fig. 8 (T6 to Q1) Huang
In regards to claim 8, Huang in view of Wang teaches shift register of claim 7, wherein the first control unit comprises:a third transistor, wherein a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first level signal terminal or the first clock signal terminal, and a second electrode of the third transistor is electrically connected to the fourth node.(fig. 8 T2 CK1 and Q1) Huang
In regards to claim 9, Huang in view of Wang teaches shift register of claim 7, wherein the second control unit comprises: a fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to the second level signal terminal, and a second electrode of the fourth transistor is electrically connected to the fourth node.(fig. 8 T6 Q1 and VGH) Huang
In regards to claim 10, Huang in view of Wang teaches shift register of claim 7, wherein the output unit comprises: a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode of the seventh transistor is electrically connected to the second level signal terminal, and a second electrode of the seventh transistor is electrically connected to the output terminal.(fig. 8 T4 and OUT1) Huang
In regards to claim 12, Huang in view of Wang teaches gate driving circuit, comprising a plurality of cascaded shift registers, wherein each of the plurality of cascaded shift registers is the shift register of any one of claims 1-to 10.(fig. 23 cascading shift registers) Huang)
In regards to claim 13, Huang in view of Wang teaches (Original) A display apparatus, comprising the gate driving circuit of claim 12. .(fig. 23 cascading shift registers)(fig. 1 2000) [0049-0055] Huang)
In regards to claim 14, Huang in view of Wang teaches register of claim 2, wherein the input sub-circuit comprises: a first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the input terminal, and a second electrode of the first transistor is electrically connected to the first node (fig. 8 T3 Huang).
In regards to claim 15, Huang in view of Wang teaches shift register of claim 2, wherein the first output sub-circuit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the first node, a first electrode of the eighth transistor is electrically connected to the first level signal terminal, and a second electrode of the eighth transistor is electrically connected to the output terminal; and a second capacitor, wherein two terminals of the second capacitor are electrically connected to the output terminal and the first node, respectively (fig. 8 (T5) VGH and Out1 Huang.)
In regards to claim 16, Huang in view of Wang teaches shift register of claim 2, wherein the second output sub-circuit comprises: a first control unit configured to transmit a first level signal at the first level signal terminal or a signal at the first clock signal terminal to a fourth node in response to a first level signal at the second node;(fig. 8 (T2) Huang)
a second control unit configured to transmit a second level signal at the second
level signal terminal to the fourth node in response to a first level signal at the first
node; and (fig. 8 (T6)) Huang)
an output unit configured to transmit a second level signal at the second level
signal terminal to the output terminal in response to a first level signal at the fourth
node.(fig. 8 T4) Huang)
In regards to claim 17, Huang in view of Wang teaches shift register of claim 3, wherein the input sub-circuit comprises: a first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the input terminal, and a second electrode of the first transistor is electrically connected to the first node. (fig. 8 T3) Huang)
In regards to claim 18, Huang in view of Wang teaches shift register of claim 3, wherein the first output sub-circuit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the first node, a first electrode of the eighth transistor is electrically connected to the first level signal terminal (fig. 8 T5 and VGH and OUT1) Huang, and a second electrode of the eighth transistor is electrically connected to the output terminal; and a second capacitor, wherein two terminals of the second capacitor are electrically connected to the output terminal and the first node, respectively. (fig. 8 (4 and C3) Huang)
In regards to claim 19, Huang in view of Wang teaches shift register of claim 3, wherein the second output sub-circuit comprises:a first control unit configured to transmit a first level signal at the first level signal terminal or a signal at the first clock signal terminal to a fourth node in response to a first level signal at the second node; (fig. 8 T2 Q1 and at least CK1) Huang) a second control unit configured to transmit a second level signal at the second level signal terminal to the fourth node in response to a first level signal at the first node; and (fig. 8 (T6)) Huang an output unit configured to transmit a second level signal at the second level signal terminal to the output terminal in response to a first level signal at the fourth node.(fig. 8 T4 and VGL)) Huang
Allowable Subject Matter
Claims 11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622
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