CTNF 19/152,430 CTNF 83087 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-7,14 and 18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ochi et al (20210296425) hereinafter, Ochi . In regards to claim 1, Ochi teaches (Currently amended) a display substrate, A display panel includes a frame region surrounding a display region. The frame region includes: a frame corner including a round corner having a curved outline in plan view of the display panel; and two sides provided so that the frame corner is sandwiched between the two sides. The two sides include: a first frame side in parallel with gate wires; and a second frame side in parallel with source wires. A gate driver and an emission driver are divided and provided to the first frame side and the second frame side . (abstract) comprising a display region (fig. 2 intersection of gate and data lines) and a non-display region (fig. 2 (outside intersection of gate and data lines)), wherein the display region is provided with pixel driving circuits arranged in an array [0010, 0029,0037], a plurality of gate line groups and a plurality of gate connection line group (fig. 2 (70s, and 73s)) , the non-display region is provided with a gate driving circuit, (fig. 2 (70s, and 73s edges)) a pixel driving circuit comprises a plurality of transistors, a gate line group is electrically connected to a gate electrode of at least one transistor and the gate driving circuit, respectively, the gate line group comprises at least one gate line, and any gate line in the gate line group extends at least partially in a first direction (fig. 6 pixel circuit [0044] and 21g), ; PNG media_image1.png 810 634 media_image1.png Greyscale a boundary of the display region comprises a plurality of arc-shaped boundaries (fig. 2 boundary arch/edge area 5a) and a plurality of straight-line boundaries (fig. 2 straight boundaries/ sides), any straight-line boundary is respectively connected to two arc-shaped boundaries (fig. 2 edges and sides connected), the non-display region comprises a frame region and a binding region which are sequentially provided in a direction away from the display region (fig. 2 top and bottom region), the binding region is located on a side of the frame region (fig 2. Top side), the frame region located outside a straight-line boundary is referred to as a straight-line frame region, the straight-line frame region comprises a first straight-line frame region and a second straight-line frame region arranged in a second direction, the first straight-line frame region is located on a side of the display region away from the binding region, the second straight-line frame region is located on a side of the display region close to the binding region, and the first direction intersects the second direction [101-109]; and PNG media_image2.png 776 1138 media_image2.png Greyscale a portion of the gate driving circuit is located in at least one of the first straight-line frame region and the second straight-line frame region (fig. 2 73s located at top and bottom), a gate connection line group is electrically connected to a local frame circuit and a gate line group connected to the local frame circuit, respectively, and the local frame circuit comprises a gate driving circuit located in at least one of the first straight- line frame region and the second straight-line frame region (fig. 2 21f) and fig. 3 (40) [0036-0040] PNG media_image3.png 522 588 media_image3.png Greyscale In regards to claim 2, Ochi teaches (display substrate according to claim 1, wherein the gate driving circuit comprises a first driving circuit to an M-th driving circuit, an m-th driving circuit comprises a plurality of cascaded m-th type shift registers (fig. 2 70, 75, 73), the gate driving circuit is divided into a plurality of shift register units [101-102] corresponding one-to-one to the plurality of gate line groups [101-104], and the shift register units are electrically connected to the corresponding gate line groups, where 1 ≤ m ≤ M; and any shift register unit comprises a first type shift register to an M-th type shift register[106], and the gate line group comprises a first gate line to an M-th gate line (fig. 8 (71)). In regards to claim 3, Ochi teaches (display substrate according to claim 2, wherein the first straight-line frame region and the second straight-line frame region are each divided into a first area and a second area which are respectively located on two sides of a first midline, and the first midline is a midline of the display region extending in the second direction; the frame region further comprises a third straight-line frame region and a fourth straight-line frame region arranged in the first direction, and the third straight-line frame region and the fourth straight-line frame region are symmetrically provided relative to the first midline; (fig. 2 (73 top and bottom)) the gate driving circuit comprises a first gate driving group comprising an (N1+1)-th shift register unit to an N2-th shift register unit, and the first gate driving group is located in at least one of the third straight-line frame region and the fourth straight-line frame region, where N1< N, N2 < N, and N2 > N1, N being a quantity of shift register units included in the gate driving circuit; and [100-106] all shift register units in the first gate driving group are arranged in the second direction, and a first type shift register to an M-th type shift register located in any shift register unit in the first gate driving group are arranged in the first direction (fig. 8 for example N=4 wherein at least 4 shift registers [100-106]. PNG media_image4.png 820 524 media_image4.png Greyscale In regards to claim 4, Ochi teaches (display substrate according to claim 3, wherein the gate driving circuit further comprises a second gate driving group comprising a first shift register unit to an N1-th shift register unit, and a third gate driving group comprising an (N2+1)-th shift register unit to an N-th shift register unit; and the second gate driving group is located in the first area of the first straight-line frame region, and the third gate driving group is located in the first area of the second straight-line frame region; (fig. 8 for example N=4 wherein at least 4 shift registers [100-106] for each quadrant alternatively, the second gate driving group is located in the second area of the first straight-line frame region, and the third gate driving group is located in the second area of the second straight-line frame region; alternatively, the second gate driving group is located in the first area and the second area of the first straight-line frame region, and the third gate driving group is located in the first area and the second area of the second straight-line frame region. fig. 8 for example N=4 wherein at least 4 shift registers [100-106] for each quadrant. Examiner is interpreting “alternatively” as an “or” operator). In regards to claim 5, Ochi teaches (display substrate according to claim 4, wherein the second gate driving group is located in the first area and the second area of the first straight-line frame region, and the second gate driving group located in the first area of the first straight-line frame region and the second gate driving group located in the second area of the first straight-line frame region are symmetrically provided with respect to the first midline; and the third gate driving group is located in the first area and the second area of the second straight-line frame region, and the third gate driving group located in the first area of the second straight-line frame region and the third gate driving group located in the second area of the second straight-line frame region are symmetrically provided relative to the first midline. (fig. 2 73 for each of the corners) In regards to claim 6, Ochi teaches (display substrate according to claim 4 or 5claim 4, wherein all shift register units located in the second gate driving group are arranged in the first direction, all shift register units located in the third gate driving group are arranged in the first direction, and a first type shift register to an M-th type shift register located in any one of the shift register units located in the second gate driving group and the third gate driving group are arranged in the second direction (fig. 2 all top are located in left to right direction and side gate drivers are located up and down direction). In regards to claim 7, Ochi teaches (display substrate according to claim 4 or 5claim 4, wherein all m-th type shift registers in the second gate driving group and the third gate driving group are referred to as an m-th type shift register group; and in the first straight-line frame region and the second straight-line frame region, all shift registers located in a shift register group of a same type are arranged in the first direction, and a first type shift register group to an M-th type shift register group are arranged in the first direction (fig. 8 71s across top and bottom) In regards to claim 14, Ochi teaches (Original) The display substrate according to claim 2, wherein a gate connection line group comprises a first gate signal connection line to an M-th gate signal connection line, and an m-th gate signal connection line is electrically connected to an m-th type shift register and an m-th gate line, respectively; and the m-th gate signal connection line extends in the second direction.(fig. 8 gate line 80 for example to 73 shift register and 71 and bends in second directions). In regards to claim 18, Ochi teaches (Currently amended) A display apparatus, comprising the display substrate according to claim 1, (see claim 1 above and fig. 1 display device of Ochi) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ochi in view of Yamada et al 2021/0020111 hereinafter, Yamada . In regards to claim 8, Ochi fails to teach (Original) The display substrate according to claim 3, wherein a rounded corner frame region comprises a first rounded corner frame region to a fourth rounded corner frame region, the first rounded corner frame region is located between the first straight-line frame region and the third straight-line frame region, the second rounded corner frame region is located between the first straight-line frame region and the fourth straight-line frame region, the third rounded corner frame region is located between the second straight-line frame region and the third straight-line frame region, and the fourth rounded corner frame region is located between the second straight-line frame region and the fourth straight-line frame region; (fig. 2 rounded corners on all four corners) the gate driving circuit further comprises a second gate driving group comprising a first shift register unit to an N1-th shift register unit, and a third gate driving group comprising an (N2+1)-th shift register unit to an N-th shift register unit; and (figs 2 and 8 for example top right corner of shift registers [101-106]) the second gate driving group is located in the first area of the first straight-line frame region Ochi fails to teach the second gate driving group is located in and the first rounded corner frame region, However, Yamada teaches the second gate driving group is located in and the first rounded corner frame region,(fig. 10 (51))Yamada PNG media_image5.png 554 772 media_image5.png Greyscale It would have been obvious to one of ordinary skill in the art to modify the teachings of Ochi to further include the second gate driving group is located in and the first rounded corner frame region as taught by Yamada in order to reduce the bezel and can be made narrower [004-005]. Therefore, Ochi in view of Yamada teaches the second gate driving group is located in and the first rounded corner frame region, and the third gate driving group is located in the first area of the second straight-line frame region and the third rounded corner frame region;[101-106] (fig. 2 73 in four corners)Ochi ,(fig. 10 (51))Yamada alternatively, the second gate driving group is located in the second area of the first straight-line frame region and the second rounded corner frame region, and the third gate driving group is located in the second area of the second straight-line frame region and the fourth rounded corner frame region; alternatively, the second gate driving group is located in the first area and the second area of the first straight-line frame region, the first rounded corner frame region and the second rounded corner frame region, and the third gate driving group is located in the first area and the second area of the second straight-line frame region, the third rounded corner frame region and the fourth rounded corner frame region. Examiner is viewing “alternatively” as an “or” operator (figs 2 and 8 for example top right corner of shift registers [101-106]). Ochi ,(fig. 10 (51))Yamada Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 9-13 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-6084. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRANT SITTA/Primary Examiner, Art Unit 2622 Application/Control Number: 19/152,430 Page 2 Art Unit: 2622 Application/Control Number: 19/152,430 Page 3 Art Unit: 2622 Application/Control Number: 19/152,430 Page 4 Art Unit: 2622 Application/Control Number: 19/152,430 Page 5 Art Unit: 2622 Application/Control Number: 19/152,430 Page 6 Art Unit: 2622 Application/Control Number: 19/152,430 Page 7 Art Unit: 2622 Application/Control Number: 19/152,430 Page 8 Art Unit: 2622 Application/Control Number: 19/152,430 Page 9 Art Unit: 2622 Application/Control Number: 19/152,430 Page 10 Art Unit: 2622 Application/Control Number: 19/152,430 Page 11 Art Unit: 2622 Application/Control Number: 19/152,430 Page 12 Art Unit: 2622 Application/Control Number: 19/152,430 Page 13 Art Unit: 2622
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