DETAILED ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/13/2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Status
Claims 1-11, 13-15, 17-20 and 22-23 are pending
Claims 17-20, 22, 23 are rejected under 35 USC § 112
Claims 1-11, 13-15, 17-20 and 22-23 are rejected under 35 USC § 103
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17, 22 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 17, line 6 states ‘wherein the storage system is the storage system according to claim 1’. This makes claim 17 a dependent claim, depending on claim 1. However, claim 1 is a storage system claim and claim 17 is a data processing method claim. Since the scope is different, the dependency of claim 17 on claim 1 makes it indefinite. Clarification is needed. For the purpose of examination examiner interprets claim 17 as an independent claim. Since the claim1 limitations are included in claim 17, the above statement may be omitted to overcome indefiniteness.
Claim 18-20 are dependent on claim 17 and hence inherit the same indefiniteness.
Claim 22, line 4 states ‘steps of the creation method for a storage system according to claim 11’. This makes claim 22 a dependent claim, depending on claim 11. However, claim 11 is a method claim and claim 22 is a device claim. Since the scope is different, the dependency of claim 22 on claim 11 makes it indefinite. Clarification is needed. For the purpose of examination examiner interprets claim 22 as an independent claim.
Claim 23, line 4 states ‘steps of the creation method for a storage system according to claim 11’. This makes claim 22 a dependent claim, depending on claim 11. However, claim 11 is a method claim and claim 23 is a non-transitory readable storage medium claim. Since the scope is different, the dependency of claim 23 on claim 11 makes it indefinite. Clarification is needed. For the purpose of examination examiner interprets claim 23 as an independent claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-11, 15 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over LI, WEI et al. (CN 110018987 B)[Li] in view of Nellans; David et al. (US 20130117503 A1)[Nellans] in view of ABULILA; Ahmed et al. (US 20200401530 A1)[Abulila] in view of Yin; Peng et al. (US 20210073092 A1)[Yin] in view of Fortin; Michael R. et al. (US 8914557 B2)[Fortin]
Regarding claim 1 Li discloses:
A storage system, wherein the storage system is an all-flash storage system, the storage system comprising (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The first storage device is connected to the second storage device, and the second storage device is connected to the third storage device. The storage medium can be one or several types of flash memory.):
[a first storage space, configured to process a non-block size aligned read/write request, wherein the first storage space is a storage space comprising persistent memory regions (PMRs) of a plurality of storage devices]
[the persistent memory regions is storage regions created by using a persistent memory region function of the storage device, the persistent memory regions of the plurality of storage devices are respectively mapped to a memory address space of an operating system, and after mapping, the plurality of persistent memory regions are concatenated into a contiguous linear storage space based on memory logical addresses thereof, the contiguous linear storage space serves as the first storage space configured to process non-block size aligned read/write requests]
a second storage space connected to the first storage space, configured to process a first block size aligned read/write request (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The first storage device is connected to the second storage device. Li: para 58 (attached espacenet translation) discloses read/write happening from/to second storage. Since no special read/write block size alignment is mentioned, it implies standard block size aligned reads and writes and is similar to the first block size); and
a third storage space connected to the second storage space, configured to process a second block size aligned read/write request, [wherein the second block size is greater than the first block size] (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The second storage device, and the second storage device is connected to the third storage device. Li: para 147 (attached espacenet translation): discloses read/write happening from/to third storage. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Larger size and lower speed indicate higher block size and is considered a second block size. Prior art Fortin is added below to support this assertion).
[a third storage space connected to the second storage space, configured to process a second block size aligned read/write request, wherein the second block size is greater than the first block size]
the first storage space, the second storage space, and the third storage space being implemented on different flash memories (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory.).
Li teaches a storage system having multiple connected storage devices and implemented on different flash memories. However, Li did not explicitly disclose, processing non-block size aligned read/write request.
Nellans discloses:
a first storage space, configured to process a non-block size aligned read/write request, wherein the first storage space is a storage space comprising persistent memory regions (PMRs) of a plurality of storage devices (Nellans: [0057] teaches a storage request module 150. The storage request module 150, is configured to service storage requests for data of the non-volatile memory device 120 where the requested data is different than a block of the non-volatile memory device 120. The storage request module 150 might receive a storage request to read a data set whose size is smaller than a block, load the block (or blocks) containing the requested data, and service the storage request by returning only the requested data set. Using a storage request module 150 to service storage requests allows a non-volatile memory device 120 to efficiently handle sub-block requests, non-block aligned requests);
Both Li and Nellans represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li in view of Nellans as it represents a combination of known prior art elements according to known methods (storage system of Li implementing non-block aligned read/write requests as used in Nellans’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Nellans [0057]).
Li/Nellans teaches a storage system having multiple connected storage devices and processing non-block size aligned read/write request. However, Li/Nellans did not explicitly teach creating persistent memory regions by using a persistent memory region function of the storage device.
Abulila discloses:
the persistent memory regions is storage regions created by using a persistent memory region function of the storage device, the persistent memory regions of the plurality of storage devices are respectively mapped to a memory address space of an operating system, and [after mapping, the plurality of persistent memory regions are concatenated into a contiguous linear storage space based on memory logical addresses thereof, the contiguous linear storage space serves as the first storage space configured to process non-block size aligned read/write requests] (Abulila [0052, 0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD) );
Both Li/Nellans and Abulila represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans in view of Abulila as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans creating a dedicated persistent memory region using persistent memory region function as used in Abulila’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Abulila [0052, 0108]).
Li/Nellans/Abulila discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device. However, Li/Nellans/Abulila did not explicitly teach concatenating the plurality of persistent memory regions into a contiguous linear storage space based on memory logical addresses.
Yin discloses:
[the persistent memory regions is storage regions created by using a persistent memory region function of the storage device, the persistent memory regions of the plurality of storage devices are respectively mapped to a memory address space of an operating system,] and after mapping, the plurality of persistent memory regions are concatenated into a contiguous linear storage space based on memory logical addresses thereof, the contiguous linear storage space serves as the first storage space configured to process non-block size aligned read/write requests (Yin: [0060], FIG. 2: teaches the GM (Global Memory) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous GM logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and it can be applied to the created persistent memory regions in Li/Nellans/Abulila’s storage system);
Both Li/Nellans/Abulila and Yin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila in view of Yin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila creating a contiguous logical memory address space by concatenating different memory regions as used in Yin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Yin [0060]).
Li/Nellans/Abulila/Yin discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device and concatenating the plurality of persistent memory regions into a contiguous linear storage space. However, Li/Nellans/Abulila/Yin did not explicitly disclose a storage system where one storage space has higher block size aligned read/write request.
Fortin discloses:
a third storage space connected to the second storage space, configured to process a second block size aligned read/write request, wherein the second block size is greater than the first block size (Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from higher speed device until it becomes a bigger size equal to a write size for the lower speed device and then the data is written/migrated to the second device. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Combining Li with Fortin we get that in Li/Nellans/Abulila/Yin/Fortin’s system the block size in third storage is larger than the block size in first storage.).
Both Li/Nellans/Abulila/Yin and Fortin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila/Yin in view of Fortin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila/Yin having larger block size for larger and slower storage space (like third storage) as used in Fortin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Fortin Col6/ln40-col6/ln61, (28)).
Regarding claim 11 A creation method for a storage system, wherein the storage system is an all-flash storage system, the method comprising (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The first storage device is connected to the second storage device, and the second storage device is connected to the third storage device. The storage medium can be one or several types of flash memory.):
[mapping persistent memory regions (PMRs) of a plurality of storage devices to a memory address space of an operating system, respectively, to create a first storage space configured to process a non-block size aligned read/write request];
[wherein the persistent memory regions are storage regions created by using a persistent memory region function of the storage device];
creating a second storage space configured to process a first block size aligned read/write request (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The first storage device is connected to the second storage device. Li: para 58 (attached espacenet translation) discloses read/write happening from/to second storage. Since no special read/write block size alignment is mentioned, it implies standard block size aligned reads and writes and is similar to the first block size); and
creating a third storage space configured to process a second block size aligned read/write request, [wherein the second block size is greater than the first block size] (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The second storage device, and the second storage device is connected to the third storage device. Li: para 147 (attached espacenet translation): discloses read/write happening from/to third storage. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Larger size and lower speed indicate higher block size. Prior art Fortin is added below to support this assertion);
wherein the creating the first storage space configured to process a non-block size aligned read/write request comprises:
[concatenating the plurality of persistent memory regions into a contiguous linear storage space based on memory logical addresses after the plurality of persistent memory regions are mapped, and using the contiguous linear storage space as the first storage space configured to process the non-block size aligned read/write request];
the first storage space, the second storage space, and the third storage space being implemented on different flash memories (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory).
Li teaches a storage system having multiple connected storage devices and implemented on different flash memories. However, Li did not explicitly disclose, processing non-block size aligned read/write request.
Nellans discloses:
mapping persistent memory regions (PMRs) of a plurality of storage devices to a memory address space of an operating system, respectively, to create a first storage space configured to process a non-block size aligned read/write request (Nellans: [0057] teaches a storage request module 150. The storage request module 150, is configured to service storage requests for data of the non-volatile memory device 120 where the requested data is different than a block of the non-volatile memory device 120. The storage request module 150 might receive a storage request to read a data set whose size is smaller than a block, load the block (or blocks) containing the requested data, and service the storage request by returning only the requested data set. Using a storage request module 150 to service storage requests allows a non-volatile memory device 120 to efficiently handle sub-block requests, non-block aligned requests);
Both Li and Nellans represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li in view of Nellans as it represents a combination of known prior art elements according to known methods (storage system of Li implementing non-block aligned read/write requests as used in Nellans’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Nellans [0057]).
Li/Nellans teaches a storage system having multiple connected storage devices and processing non-block size aligned read/write request. However, Li/Nellans did not explicitly teach creating persistent memory regions by using a persistent memory region function of the storage device.
Abulila discloses:
wherein the persistent memory regions are storage regions created by using a persistent memory region function of the storage device (Abulila [0052, 0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD));
Both Li/Nellans and Abulila represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans in view of Abulila as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans creating a dedicated persistent memory region using persistent memory region function as used in Abulila’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Abulila [0052, 0108]).
Li/Nellans/Abulila discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device. However, Li/Nellans/Abulila did not explicitly teach concatenating the plurality of persistent memory regions into a contiguous linear storage space based on memory logical addresses.
Yin discloses:
concatenating the plurality of persistent memory regions into a contiguous linear storage space based on memory logical addresses after the plurality of persistent memory regions are mapped, and using the contiguous linear storage space as the first storage space configured to process the non-block size aligned read/write request (Yin: [0060], FIG. 2: teaches the GM (Global Memory) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous GM logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and it can be applied to the created persistent memory regions in Li/Nellans/Abulila’s storage system);
Both Li/Nellans/Abulila and Yin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila in view of Yin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila creating a contiguous logical memory address space by concatenating different memory regions as used in Yin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Yin [0060]).
Li/Nellans/Abulila/Yin discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device and concatenating the plurality of persistent memory regions into a contiguous linear storage space. However, Li/Nellans/Abulila/Yin did not explicitly disclose a storage system where one storage space has higher block size aligned read/write request.
Fortin discloses:
creating a third storage space configured to process a second block size aligned read/write request, wherein the second block size is greater than the first block size (Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from higher speed device until it becomes a bigger size equal to a write size for the lower speed device and then the data is written/migrated to the second device. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Combining Li with Fortin we get that in Li/Nellans/Abulila/Yin/Fortin’s system the block size in third storage is larger than the block size in first storage.).
Both Li/Nellans/Abulila/Yin and Fortin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila/Yin in view of Fortin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila/Yin having larger block size for larger and slower storage space (like third storage) as used in Fortin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Fortin Col6/ln40-col6/ln61, (28)).
Regarding claim 2 Li/Nellans/Abulila/Yin/Fortin discloses:
The storage system according to claim 1, wherein the first storage space is a storage space of a storage-class memory (Li: para 51 (attached espacenet translation): teaches the first storage device mainly including a processing unit and a storage medium. The storage medium may be any one or more of solid state hard disk (SSD) disk, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), flash memory and so on. wherein the number of processing unit and storage medium depends on the configuration and type of the first storage device. Since applicant did not define storage-class memory, examiner considers all the above mentioned storage medium as storage-class memory.).
Regarding claim 3 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the storage device is a solid-state drive (Li: para 51 (attached espacenet translation): teaches the first storage device mainly including a processing unit and a storage medium. The storage medium may be any one or more of solid state hard disk (SSD)).
Regarding claim 4 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the first storage space is a contiguous linear storage space comprising persistent memory regions of the plurality of storage devices (Abulila [0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD). Abulila [0052]: teaches storage system 34 is provided for reading from and writing to a non-volatile memory called a “hard drive”. So, Abulila teaches creating persistent memory using a portion of non-volatile memory. Yin: [0060], FIG. 2: teaches the GM (Global Memory) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and hence Li/Nellans/Abulila/Yin/Fortin’s storage system contains first storage space which is a contiguous linear storage space comprising persistent memory regions.).
Regarding claim 5 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the first storage space is further configured to aggregate data of a plurality of bytes into data of the first block size and migrate the data to the second storage space (Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from first device (similar to first storage space) until it becomes a bigger size equal to a write size for another/second device (similar to second storage space) and then the data is written/migrated to the second device.).
Regarding claim 6 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the second storage space is further configured to aggregate a plurality of pieces of data of the first block size into data of the second block size and migrate the data to the third storage space (Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from first device (similar to second storage space) until it becomes a bigger size equal to a write size for another/second device (similar to third storage space) and then the data is written/migrated to the second device.).
Regarding claim 9 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the first storage space is configured to store byte-scale data (Fortin: Col4/ln61-col5/ln9: (18): teaches flash memory 152 can be read or programmed a byte or a word at a time in a random access fashion. Starting with a freshly erased block, any byte within that block can be programmed.);
the second storage space is configured to store KB-scale data (Fortin: Col6/ln40-col6/ln61, (28): teaches the preferred write size may be a multiple of 2 raised to a power such as is one of 128 kb, 256 kb, and 512 kb.); and
the third storage space is configured to store MB-scale data (Fortin: Col6/ln40-col6/ln61, (28): teaches the preferred write size may be a multiple of 2 raised to a power such as is one of 128 kb, 256 kb, and 512 kb. Fortin provided example of the preferred write size to be 2 raised to a power which includes write size of 1 MB, 2 MB 4 MB etc as well.).
Regarding claim 10 Li/Nellans/Abulila/Yin/Fortin discloses: The storage system according to claim 1, wherein the first storage space is a contiguous storage space comprising the persistent memory regions of the plurality of storage devices, the persistent memory regions are storage regions created by using a persistent memory region function of the storage device, and the first storage space, the second storage space, and the third storage space are implemented on different flash memories (Abulila [0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD). Abulila [0052]: teaches storage system 34 is provided for reading from and writing to a non-volatile memory called a “hard drive”. So, Abulila teaches creating persistent memory using a portion of non-volatile memory. Yin: [0060], FIG. 2: teaches the GM (Global Memory) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous GM logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and it can be applied to the created persistent memory regions in Li/Nellans/Abulila/Yin/Fortin’s storage system. Li:para 49, 51 (attached espacenet translation):FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory. Li also teaches the first storage device is connected to the second storage device, and the second storage device is connected to the third storage device. The storage medium can be one or several types of flash memory which indicates they are separate entity and each can be of different types of flash memory.).
Regarding claim 15 Li/Nellans/Abulila/Yin/Fortin discloses: The creation method for a storage system according to claim 11, wherein the storage system is an all-flash storage system, the persistent memory regions are storage regions created by using a persistent memory region function of the storage device, and the first storage space, the second storage space, and the third storage space are implemented on different flash memories (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system where the storage medium can be one or several types of flash memory. Abulila [0052, 0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD)).
Regarding claim 22 Li/Nellans/Abulila/Yin/Fortin discloses: An electronic device, comprising:
a memory, configured to store a computer program; and a processor, configured to implement, when executing the computer program, steps of the creation method for a storage system according to claim 11 (Abulila: [0049], FIG. 1, teaches an electronic device, comprising one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16. Since it is a processor, it is capable of executing any computer program, including the steps of the creation method for a storage system according to claim 11.).
This is a device claim corresponding to the method claim 11 and is rejected for the same reasons mutatis mutandis.
Regarding claim 23, this is a non-transitory readable storage medium claim corresponding to method claim 11 and is rejected for the same reasons mutatis mutandis.
Claims 7-8 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over LI, WEI et al. (CN 110018987 B)[Li] in view of Nellans; David et al. (US 20130117503 A1)[Nellans] in view of ABULILA; Ahmed et al. (US 20200401530 A1)[Abulila] in view of Yin; Peng et al. (US 20210073092 A1)[Yin] in view of Fortin; Michael R. et al. (US 8914557 B2)[Fortin] further in view of Madabhushi; Rajiv (US 20190332298 A1)[ Madabhushi]
Regarding claim 7 Li/Nellans/Abulila/Yin/Fortin discloses all the limitation of claim 1. However, Li/Nellans/Abulila/Yin/Fortin did not explicitly disclose that the storage space is single level cell (SLC) or a multi level cell (MLC).
Madabhushi discloses: The storage system according to claim 1, wherein the second storage space is a single level cell (SLC) or a multi level cell (MLC) (Madabhushi: claim 5: teaches the first type of data storage configuration is a single-level cell (SLC) type, the second type of data storage configuration is a multi-level cell (MLC) type, and the third type of data storage configuration is a triple-level cell (TLC) type or a quad-level cell (QLC) type. So, storages being built as SLC/MLC are well known in the art and is taught by Madabhushi and can be applied to build/configure second storage space.).
Both Li/Nellans/Abulila/Yin/Fortin and Madabhushi represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila/Yin/Fortin in view of Madabhushi as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila/Yin/Fortin having storage space configured SLC/MLC/TLC/QLC type cells as used in Madabhushi’s system) to develop a more efficient and larger capacity storage system leading to a more efficient information processing system (see also Madabhushi [0029-0030, 0036], claim 5).
Regarding claim 8 Li/Nellans/Abulila/Yin/Fortin discloses all the limitation of claim 1. However, Li/Nellans/Abulila/Yin/Fortin did not explicitly disclose that the storage space is single level cell (TLC) or a multi level cell (QLC).
Madabhushi discloses:
The storage system according to claim 1, wherein the third storage space is a triple level cell (TLC), or a quad level cell(QLC), or a penta level cell (PLC) (Madabhushi: claim 5: teaches the first type of data storage configuration is a single-level cell (SLC) type, the second type of data storage configuration is a multi-level cell (MLC) type, and the third type of data storage configuration is a triple-level cell (TLC) type or a quad-level cell (QLC) type. So, storages being built as QLC/TLC are well known in the art and is taught by Madabhushi and can be applied to build/configure third storage space).
Regarding claim 13 Li/Nellans/Abulila/Yin/Fortin discloses: The creation method for a storage system according to claim 11, wherein the creating a second storage space configured to process a first block size aligned read/write request comprises (Li: para 58 (attached espacenet translation) discloses read/write happening from/to second storage. Since no special read/write block size alignment is mentioned, it implies standard block size aligned reads and writes and is similar to the first block size):
Li/Nellans/Abulila/Yin/Fortin discloses all the limitation of claim 11. However, Li/Nellans/Abulila/Yin/Fortin did not explicitly disclose that the storage space is single level cell (SLC) or a multi level cell (MLC).
Madabhushi discloses:
creating a single level cell or a multi level cell configured to process the read/write request that is aligned with the first block size (Madabhushi: claim 5: teaches the first type of data storage configuration is a single-level cell (SLC) type, the second type of data storage configuration is a multi-level cell (MLC) type, and the third type of data storage configuration is a triple-level cell (TLC) type or a quad-level cell (QLC) type. So, storages being built as SLC/MLC are well known in the art and is taught by Madabhushi and can be applied to build/configure second storage space.).
Regarding claim 14 Li/Nellans/Abulila/Yin/Fortin discloses: The creation method for a storage system according to claim 11, wherein the creating a third storage space configured to process a second block size aligned read/write request comprises (Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Larger size and lower speed indicate higher block size and is considered a second block size. Prior art Fortin is added below to support this assertion):
Li/Nellans/Abulila/Yin/Fortin discloses all the limitation of claim 1. However, Li/Nellans/Abulila/Yin/Fortin did not explicitly disclose that the storage space is single level cell (TLC) or a multi level cell (QLC).
Madabhushi discloses:
creating a triple level cell (TLC), or a quad level cell (QLC), or a penta level cell (PLC) configured to process the second block size aligned read/write request (Madabhushi: claim 5: teaches the first type of data storage configuration is a single-level cell (SLC) type, the second type of data storage configuration is a multi-level cell (MLC) type, and the third type of data storage configuration is a triple-level cell (TLC) type or a quad-level cell (QLC) type. So, storages being built as SLC/MLC are well known in the art and is taught by Madabhushi and can be applied to build/configure second storage space).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over LI, WEI et al. (CN 110018987 B)[Li] in view of Nellans; David et al. (US 20130117503 A1)[Nellans] in view of ABULILA; Ahmed et al. (US 20200401530 A1)[Abulila] in view of Yin; Peng et al. (US 20210073092 A1)[Yin] in view of Fortin; Michael R. et al. (US 8914557 B2)[Fortin] further in view of SUN, Cheng-si et al. (CN 113778906 A)
Regarding claim 17 Li discloses: A data processing method, comprising:
[in response to receiving a read/write request, determining an alignment mode of the read/write request];
[responding to the read/write request by using a first storage space of a storage system in a case that the read/write request is non-block size aligned read/write request, wherein the storage system is the storage system according to claim 1];
the storage system is an all-flash storage system (Li:para 49, 51 (attached espacenet translation):FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory), and
[the first storage space is specifically a contiguous storage space comprising persistent memory regions (PMRs) of a plurality of storage devices, the persistent memory regions being storage regions created by using a persistent memory region function of the storage device];
responding to the read/write request by using a second storage space of the storage system in a case that the read/write request is a first block size aligned read/write request (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The first storage device is connected to the second storage device. Li: para 58 (attached espacenet translation) discloses read/write happening from/to second storage. Since no special read/write block size alignment is mentioned, it implies standard block size aligned reads and writes and is similar to the first block size); and
responding to the read/write request by using a third storage space of the storage system in a case that the read/write request is second block size aligned read/write request, [wherein the second block size is greater than the first block size] (Li: para 49, 51 (attached espacenet translation), FIG. 1: discloses a schematic structural diagram of a storage system. The system includes: a first storage device, a second storage device, and a third storage device. The second storage device, and the second storage device is connected to the third storage device. Li: para 147 (attached espacenet translation): discloses read/write happening from/to third storage. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Larger size and lower speed indicate higher block size. Prior art Fortin is added below to support this assertion.);
the first storage space, the second storage space, and the third storage space being implemented on different flash memories (Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory).
Li teaches a storage system having multiple connected storage devices and implemented on different flash memories. However, Li did not explicitly disclose, processing non-block size aligned read/write request.
Nellans discloses:
responding to the read/write request by using a first storage space of a storage system in a case that the read/write request is non-block size aligned read/write request, wherein the storage system is the storage system according to claim 1 (Nellans: [0057] teaches a storage request module 150. The storage request module 150, is configured to service storage requests for data of the non-volatile memory device 120 where the requested data is different than a block of the non-volatile memory device 120. The storage request module 150 might receive a storage request to read a data set whose size is smaller than a block, load the block (or blocks) containing the requested data, and service the storage request by returning only the requested data set. Using a storage request module 150 to service storage requests allows a non-volatile memory device 120 to efficiently handle sub-block requests, non-block aligned requests);
Both Li and Nellans represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li in view of Nellans as it represents a combination of known prior art elements according to known methods (storage system of Li implementing non-block aligned read/write requests as used in Nellans’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Nellans [0057]).
Li/Nellans teaches a storage system having multiple connected storage devices and processing non-block size aligned read/write request. However, Li/Nellans did not explicitly teach creating persistent memory regions by using a persistent memory region function of the storage device.
Abulila discloses:
[the first storage space is specifically a contiguous storage space comprising persistent memory regions (PMRs) of a plurality of storage devices], the persistent memory regions being storage regions created by using a persistent memory region function of the storage device (Abulila [0052, 0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD));
Both Li/Nellans and Abulila represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans in view of Abulila as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans creating a dedicated persistent memory region using persistent memory region function as used in Abulila’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Abulila [0052, 0108]).
Li/Nellans/Abulila discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device. However, Li/Nellans/Abulila did not explicitly teach concatenating the plurality of persistent memory regions into a contiguous linear storage space based on memory logical addresses.
Yin discloses:
the first storage space is specifically a contiguous storage space comprising persistent memory regions (PMRs) of a plurality of storage devices, [the persistent memory regions being storage regions created by using a persistent memory region function of the storage device] (Yin: [0060], FIG. 2: teaches the Global Memory (GM) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous GM logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and it can be applied to the created persistent memory regions in Li/Nellans/Abulila’s storage system);
Both Li/Nellans/Abulila and Yin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila in view of Yin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila creating a contiguous logical memory address space by concatenating different memory regions as used in Yin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Yin [0060]).
Li/Nellans/Abulila/Yin discloses a storage system having multiple connected storage devices and processing non-block size aligned read/write request and creating persistent memory regions by using a persistent memory region function of the storage device and concatenating the plurality of persistent memory regions into a contiguous linear storage space. However, Li/Nellans/Abulila/Yin did not explicitly disclose a storage system where one storage space has higher block size aligned read/write request.
Fortin discloses:
responding to the read/write request by using a third storage space of the storage system in a case that the read/write request is second block size aligned read/write request, wherein the second block size is greater than the first block size (Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from higher speed device until it becomes a bigger size equal to a write size for the lower speed device and then the data is written/migrated to the second device. Li para 54-56 (attached espacenet translation): teaches third storage is larger than the first storage device and could be of lower speed. Combining Li with Fortin we get that in Li/Nellans/Abulila/Yin/Fortin’s system the block size in third storage is larger than the block size in first storage.).
Both Li/Nellans/Abulila/Yin and Fortin represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila/Yin in view of Fortin as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila/Yin having larger block size for larger and slower storage space (like third storage) as used in Fortin’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Fortin Col6/ln40-col6/ln61, (28)).
Li/Nellans/Abulila/Yin/Fortin discloses all the limitation of claim 17 except determining read/write alignment mode.
Sun discloses:
in response to receiving a read/write request, determining an alignment mode of the read/write request (Sun: para 111 (attached translated copy): teaches determining alignment/non-alignment read request mode);
Both Li/Nellans/Abulila/Yin/Fortin and Sun represent works within the same field of endeavor, namely information processing devices focusing on storage technologies. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Li/Nellans/Abulila/Yin/Fortin in view of Sun as it represents a combination of known prior art elements according to known methods (storage system of Li/Nellans/Abulila/Yin/Fortin determining read alignment mode as used in Sun’s system) to develop a more efficient storage system leading to a more efficient information processing system (see also Sun para 111).
Regarding claim 18 Li/Nellans/Abulila/Yin/Fortin/Sun discloses: The data processing method according to claim 17, further comprising: aggregating data of a plurality of bytes in the first storage space into data of the first block size and migrating the data to the second storage space (Fortin: Col4/ln61-col5/ln9: (18): teaches flash memory 152 can be read or programmed a byte or a word at a time in a random access fashion. Starting with a freshly erased block, any byte within that block can be programmed. Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from first device (similar to first storage space) until it becomes a bigger size equal to a write size for another/second device (similar to second storage space) and then the data is written/migrated to the second device).
Regarding claim 19 Li/Nellans/Abulila/Yin/Fortin/Sun discloses: The data processing method according to claim 17, further comprising: aggregating a plurality of pieces of data of the first block size in the second storage space into data of the second block size and migrating the data to the third storage space (Fortin: Col4/ln61-col5/ln9: (18): teaches flash memory 152 can be read or programmed a byte or a word at a time in a random access fashion. Starting with a freshly erased block, any byte within that block can be programmed. Fortin: Col6/ln40-col6/ln61, (28): teaches collecting/aggregating data from first device (similar to second storage space) until it becomes a bigger size equal to a write size for another/second device (similar to third storage space) and then the data is written/migrated to the second device).
Regarding claim 20 Li/Nellans/Abulila/Yin/Fortin/Sun discloses: The data processing method according to claim 17, wherein the storage system is an all-flash storage system, the first storage space is a contiguous storage space comprising persistent memory regions of a plurality of storage devices, the persistent memory regions are storage regions created by using a persistent memory region function of the storage device, and the first storage space, the second storage space, and the third storage space are implemented on different flash memories (Abulila [0052, 0108]: teaches creating a dedicated persistent memory region with a provided function. All of the virtual addresses in the persistent memory region are mapped to the address space of the memory medium 540 (e.g., an SSD). Yin: [0060], FIG. 2: teaches the Global Memory (GM) segments 220a-n being logically concatenated or viewed in the aggregate as forming one contiguous GM logical address space of a distributed GM. So, Yin teaches concatenating the plurality of memory regions into a contiguous storage space based on memory logical addresses and it can be applied to the created persistent memory regions in Li/Nellans/Abulila’s storage system. Li: para 49, 51 (attached espacenet translation): FIG. 1 discloses a schematic structural diagram of a storage system. The storage medium can be one or several types of flash memory).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is recorded in pe2e_search_note.pdf and is attached as OA.APPENDIX.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138