DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 14 August 2025 and 7 July 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 5 and 21 are objected to because of the following informalities:
In claim 5, lines 2-3, “has been invalid” should read “is invalid”.
In claim 21, line 2, “has been invalid” should read “is invalid”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3, 5, 17, 19, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 5, 19, and 21 each include the phrase “one or more pieces of information of… and”. It is unclear whether this should indicate one or more pieces of information of each item listed, or one or more pieces of information selected from the items listed. For the purposes of compact prosecution, the claims have been examined under the broadest reasonable interpretation, wherein one or more pieces of information are selected from the items listed. Applicant is recommended to amend the claims to clarify this language.
Claim 17 recites the limitation "the physical machine" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Illikkal et al (U.S. Patent Pub. No. 2019/0005176), hereinafter referred to as Illikkal.
In regard to claim 1, Illikkal teaches a data transmission method (¶ 0038-0039 method for low latency memory and storage access i.e. data transmission), applied to a data processing unit (¶ 0040; Fig. 2 MCP 202), wherein the data processing unit is assembled on a physical machine (¶ 0095 embodiments may be exemplified by physical system such as Fig. 11), the data processing unit comprises a processor and a programmable logic device (¶ 0040, lines 1-5 MCP includes processor and FPGA), and the method comprises: sending, by the processor, a data input request to the programmable logic device (¶ 0045, lines 1-6; Fig. 2 system agent 214 in processor sends a memory request to FPGA agent 206), wherein the data input request indicates to transmit first data in a first storage server to a memory of the physical machine (¶ 0065 FPGA may receive and process request to write data to memory from storage-as-memory; ¶ 0058 storage-as-memory may be disaggregated networked storage devices i.e. storage servers); obtaining, by the programmable logic device, according to the data input request, a response packet containing the first data from the first storage server (¶ 0065 lines 10-18 FPGA receives data in its accelerator circuits); and writing, by the programmable logic device, the first data into the memory of the physical machine (¶ 0065, lines 15-18 processed data may be written to memory) in a case of determining that the response packet meets an input condition (Fig. 9 PCIe descriptor includes ordering field 916; ¶ 0085 writes may be restricted or allowed based on ordering type).
As for claim 2, the previously cited references teach the method of claim 1. Additionally, Illikkal teaches an embodiment wherein the method further comprises: extracting, by the programmable logic device, packet description information from a specified field of the response packet (Fig. 5A FPGA manages all connected memory; ¶ 0057 FPGA may use PCIe for memory interfacing; Fig. 9, ¶ 0082 PCIe transactions include an identifier field), wherein the specified field is configured by the first storage server according to a specified communication protocol agreed between the first storage server and the programmable logic device (¶ 0077 PCIe includes request and response packets, therefore a response packet will have an identifier field configured by the responding storage according to the PCIe protocol); and determining, by the programmable logic device, that the data input request meets the input condition in a case of finding check rule information corresponding to the data input request and the packet description information matches the check rule information, wherein the check rule information corresponding to the data input request is generated and sent by the processor to the programmable logic device (¶ 0083 identifier field is generated by requesting agent (i.e. the processor) and is used to uniquely match requests to responses (¶ 0082), therefore complete transaction success must functionally rely on a determining a correct identifier for the transaction response).
As for claim 15, Applicant is directed to the rejection of claim 1 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 16, Applicant is directed to the rejection of claim 1 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 17, Applicant is directed to the rejection of claim 1 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 18, Applicant is directed to the rejection of claim 2 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Illikkal in view of Butler et al (U.S. Patent Pub. No. 4,654,654), hereinafter referred to as Butler.
As for claim 3, the previously cited references teach the method of claim 2. Additionally, Illikkal discloses known techniques wherein the packet description information comprises one or more pieces of information of an identifier, a target memory address, and a data length of the data input request (¶ 0083 identifier field is generated by requesting agent (i.e. the processor) and is used to uniquely match requests to responses (¶ 0082)). The previously cited references do not teach that the programmable logic device writes the first data into the memory of the physical machine in a direct memory access manner, however Butler Fig. 2 teaches a network interface 153 which may utilize DMA module 154, easily applicable to the interface FPGA of Illikkal Fig. 5A by one of ordinary skill in the art. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Butler in order to utilize DMA for local transactions and address the issue of processing overhead for data transaction routing (Column 2, lines 24-39 disclose issues with prior art systems to be addressed by the disclosure).
As for claim 4, the previously cited references teach the method of claim 2. The previously cited references do not teach the remaining limitations of claim 4. However, Butler teaches an embodiment comprising: deleting, by the programmable logic device, the check rule information corresponding to the data input request locally in a case of determining that the packet description information does not match the check rule information or after writing the first data into the memory (Column 7 lines 35-37 packets are locally discarded (which would include headers i.e. check rule information) if not destined for node i.e. incorrect identifier; lines 46-50 packets are locally discarded after transmission to node storage i.e. written to memory in the case of a write). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Butler in order to discard unneeded packet information and address the issue of processing overhead for data transaction routing (Column 2, lines 24-39 disclose issues with prior art systems to be addressed by the disclosure).
As for claim 5, the previously cited references teach the method of claim 2. The previously cited references do not teach the remaining limitations of claim 5. However, Butler teaches an embodiment comprising: sending, by the processor, in a case of determining that the data input request has been invalid, a deletion instruction for the check rule information corresponding to the data input request to the programmable logic device, to enable the programmable logic device to delete the check rule information corresponding to the data input request locally (Column 10, lines 6-16 host process (e.g. requesting agent of Illikkal) is notified of failed packet reception and may request retransmission, which would functionally include deleting and replacing existing packet data for that packet), wherein the check rule information comprises one or more pieces of information of an identifier, a target memory address, a data length, a request delivery time, and request valid duration of the data input request (Fig. 3; Column 11 lines 21-23 packets include destination address). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Butler in order to discard unneeded packet information and address the issue of processing overhead for data transaction routing (Column 2, lines 24-39 disclose issues with prior art systems to be addressed by the disclosure).
As for claim 6, the previously cited references teach the method of claim 2. The previously cited references do not teach the remaining limitations of claim 6. However, Butler teaches an embodiment wherein the determining, by the programmable logic device, that the data input request meets the input condition in a case of finding check rule information corresponding to the data input request and the packet description information matches the check rule information comprises: extracting, by the programmable logic device, error detection check information from the response packet; performing, by the programmable logic device, error detection on the first data in the response packet based on the error detection check information (Column 9 line 59 to Column 10 line 1 packets include error checking information; Fig. 3 this includes all packet types); and determining, by the programmable logic device, that the data input request meets the input condition in a case of finding the check rule information corresponding to the data input request, the packet description information matches the check rule information, and the first data passes the error detection (Column 10 lines 1-5 packets are discarded on error check fail; Column 7 lines 35-37 packets are discarded on node ID check fail (i.e. check rule information from processor); Column 7 lines 46-50 after processing (i.e. receiving and error checking), data may be written (input)). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Butler in order to discard malformed packet information and address the issue of processing overhead for data transaction routing (Column 2, lines 24-39 disclose issues with prior art systems to be addressed by the disclosure).
As for claim 19, Applicant is directed to the rejection of claim 3 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 20, Applicant is directed to the rejection of claim 4 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 21, Applicant is directed to the rejection of claim 5 above, as the claims are directed to the same limitations and therefore rejected on the same rationale.
Claims 7 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Illikkal in view of Chan et al (U.S. Patent Pub. No. 2022/0200961), hereinafter referred to as Chan.
As for claim 7, the previously cited references teach the method of claim 2. The previously cited references do not teach the remaining limitations of claim 7. However, Chan teaches an embodiment wherein the determining, by the programmable logic device, that the data input request meets the input condition in a case of finding check rule information corresponding to the data input request and the packet description information matches the check rule information comprises: obtaining, by the programmable logic device, error detection check information provided by the processor for the check rule information corresponding to the data input request (¶ 0045; Figs. 2-3 PLD 140 may receive packets from server processor including a proprietary header checksum (check rule information) in the payload and a CRC code (payload error detection)); performing, by the programmable logic device, error detection on the check rule information based on the error detection check information (¶ 0045 lines 1-10, PLD receives packet for filtering based on proprietary header, would functionally include error checking to ensure the correct payload data and therefore proprietary header is received); and determining, by the programmable logic device, that the data input request meets the input condition in a case of finding the check rule information corresponding to the data input request, the packet description information matches the check rule information, and the check rule information passes the error detection (¶ 0045 lines 1-10 determination is based on identified proprietary header; lines 12-17 checksum is used to verify proprietary header; error detection must succeed or checksum verification will fail). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chan in order to validate individual packets and prevent device infection from unsecured sources (¶ 0004)
As for claim 10, the previously cited references teach the method of claim 1. The previously cited references do not explicitly teach the remaining limitations of claim 10. However, Chan teaches an embodiment comprising: sending, by the processor, a data output request to the programmable logic device, wherein the data output request indicates to transmit second data in the memory of the physical machine to a second storage server (¶ 0045 lines 1-6 PLD may receive packet to output from server i.e. processor and determine to output to another device e.g. networked storage of Illikkal); reading, by the programmable logic device, the second data from the memory of the physical machine according to the data output request (packet must functionally be read from server memory into PLD for PLD to examine); and sending, by the programmable logic device, the second data to the second storage server in a case of determining that the second data meets an output condition (¶ 0045 lines 5-10 packet may be output according to filtering rule). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chan in order to securely transmit data to other nodes via the PLD and prevent device infection from unsecured sources (¶ 0004).
As for claim 11, the previously cited references teach the method of claim 10. The previously cited references do not explicitly teach the remaining limitations of claim 11. However, Chan teaches an embodiment wherein the sending, by the programmable logic device, the second data to the second storage server comprises: obtaining, by the programmable logic device, from the processor, a protocol field that is used for supporting a storage protocol and corresponds to the data output request (¶ 0042 proprietary header synchronization word is used for unidirectional protocol (see ¶ 0041)); constructing, by the programmable logic device, an output packet according to the second data and the protocol field in a case that the protocol field meets an integrity requirement (¶ 0045 lines 12-19 synchronization word is verified before sending; if combined with Illikkal FPGA may construct/deconstruct packets); and sending, by the programmable logic device, the output packet to the second storage server (¶ 0045 lines 5-8; if combined with Illikkal device may be networked storage).
As for claim 12, the previously cited references teach the method of claim 11. Additionally, Chan teaches obtaining, by the programmable logic device, data description information provided by the processor for the data output request; determining, by the programmable logic device, that the second data meets the output condition in a case that the second data matches the data description information (¶ 0045 filtering rule (data description info) is used to match packet format; ¶ 0047 PLD may receive filtering rule from processor); obtaining, by the programmable logic device, error detection check information provided by the processor for the protocol field; performing, by the programmable logic device, error detection on the protocol field based on the error detection check information; and determining, by the programmable logic device, that the protocol field meets the integrity requirement in a case that the protocol field passes the error detection (¶ 0045 lines 12-19 proprietary header (protocol field) checksum (error detection info) is used to determine whether to send packet).
As for claim 13, The previously cited references teach the method of claim 11. Additionally, Illikkal teaches calculating, by the programmable logic device, error detection check information for the second data; and configuring the error detection check information corresponding to the second data in the output packet (¶ 0087 lines 10-11 CRC is generated and applied to packets before transmission i.e. in the FPGA (see Fig. 8 protocol stack connected to processor and external devices; Fig. 5A FPGA acting as protocol stack)).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Illikkal in view of Karumbunathan et al (U.S. Patent Pub. No. 2020/0159421), hereinafter referred to as Karumbunathan. The previously cited references teach the method of claim 1. The previously cited references do not explicitly teach the remaining limitations of claim 8. However, Karumbunathan teaches an embodiment wherein the physical machine is any cloud server in a computing cluster (Fig. 1A Computing devices 164), and the first storage server is any storage server in a storage cluster (Fig. 1A Storage arrays 102); and a virtual machine and a virtual storage device are run on the physical machine (¶ 0029 computing devices serve clients and may be and embodied as a server in a datacenter; ¶ 0115 users i.e. client devices may utilize virtual machines including virtual storage devices), the virtual storage device is generated by performing storage virtualization on the storage cluster (¶ 0124), and the method further comprises: obtaining, by the processor, a read request initiated by the virtual machine running on the physical machine (¶ 0308 client running VM may request data i.e. read request), wherein the read request comprises a target physical address to which the read request is pointed in a physical address space corresponding to the virtual storage device (¶ 0133 storage controller applications may interact with the cloud storage as physical devices and send the same messages as physical controllers, which would include requests with target physical addresses which correspond to the virtualized storage); and determining, by the processor, a storage server corresponding to the target physical address in the storage cluster as the first storage server (¶ 0081 data is located by consulting storage node having authority over a data segment i.e. storage server is determined). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Karumbunathan in order to benefit from large scale virtualization and techniques for persistent reliable cloud data storage (¶ 0307 cloud-based storage system persists all data and manages retention for instances).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Illikkal in view of Karumbunathan and Cela (U.S. Patent Pub. No. 2018/0278583). The previously cited references teach the method of claim 8. The previously cited references do not teach the remaining limitations of claim 9. However, Cela teaches an embodiment comprising: extracting, by the programmable logic device, a protocol field used for supporting a storage protocol from the response packet; sending the extracted protocol field to the processor (¶ 0067; Fig. 4C session handler 167 in programmable hardware may send validity request and partial header (protocol field) to processor applications when packet is received); and sending, by the processor, a valid instruction for the first data to the memory in a case of determining that the protocol field meets a specified requirement (¶ 0069), to enable the memory to validate the first data written by the programmable logic device (¶ 0070 payload is extracted and transmitted to application i.e. stored in some system memory for applications). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Cela in order to verify packets using additional processing and address communication overhead between an FPGA and processor (¶ 0007-0008).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Semisaga discloses the structure of PCIe packets as of the date of publishing of Illikkal, which takes advantage of typical PCIe formats.
Atta et al discloses techniques for virtualization in a system having programmable logic devices.
Alachiotis et al discloses techniques for improving efficiency of communication between FPGAs and general processors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
Prosecution Insights