DETAILED ACTION
This is a first office action in response to application 19/161,330 filed 09/02/2025, in which claims 1-11 are presented for examination. A preliminary amendment was filed concurrently therewith which provides amendments to claims 10 and adds new claims 12-20.
Currently claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5 and 9 are objected to because of the following informalities: The claims recite “a second gate control signal” twice in each of the identified claims. As this appears to be the intention this is the same signal, The Office suggest changing the second instance of “a” to “the”. Should this be incorrect, The Office suggests providing a different naming convention for this signal. Appropriate correction is required.
Claim 17 are objected to because of the following informalities: The claims recite “a gate control signal” twice in each of the identified claims. As this appears to be the intention this is the same signal, The Office suggest changing the second instance of “a” to “the”. Should this be incorrect, The Office suggests providing a different naming convention for this signal. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-11, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by No et al. U.S. Patent Application Publication No. 2023/0368736 A1 hereinafter No.
Consider Claim 1:
No discloses a display panel, comprising (No, [0068], “The display apparatus 10 may include a display panel, and the display panel may include a substrate.)
a plurality of kinds of gate drive circuits, and (No, [0058], “Referring to FIG. 1, the display apparatus 10 may include a pixel unit 110, a gate driving circuit 130, a data driving circuit 150, a power supply circuit 170, and a controller 190.”)
further comprising a plurality of sub-pixels arranged in an array, wherein a sub-pixel of the plurality of sub-pixels comprises a pixel drive circuit and a light emitting element, the pixel drive circuit comprises a plurality of transistors, (No, [0060], “The pixels PX may be arranged in various shapes, such as stripe arrangement, PenTile® arrangement, mosaic arrangement, and the like. The pixel unit 110 may be arranged in a display area of a substrate. Each of the pixels PX may include an organic light-emitting diode (OLED) as a display element (a light-emitting device), and the organic light-emitting diode (OLED) may be connected to a pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor.”)
wherein, the plurality of kinds of gate drive circuits are configured to output a plurality of kinds of gate drive signals to the plurality of transistors in the pixel drive circuit, wherein each kind of gate drive circuit outputs one kind of gate drive signal, the plurality of kinds of gate drive signals are divided into at least two groups, (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.”)
high-level voltages of gate drive signals in a same group are the same, and low-level voltages of gate drive signals in a same group are the same; high-level voltages of gate drive signals in different groups are different, and/or low-level voltages of gate drive signals in different groups are different; and (No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
the pixel drive circuit is configured to receive the plurality of kinds of gate drive signals and drive the light emitting element to emit light according to the received plurality of kinds of gate drive signals. (No, [0080], “In an embodiment, the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be respectively supplied to the first through sixth gate lines GL1 to GL6 of each pixel row at a certain timing. In another embodiment, the first gate signal GW may be sequentially supplied to the first gate line GL1 of each pixel row at a certain timing, and the second through sixth gate signals GI, GC, EM1, EM2, and GC2 may be sequentially and respectively supplied to second through sixth gate lines GL2 to GL6 of two pixel rows and may be sequentially supplied in the unit of two pixel rows. For example, the fifth gate driving circuit may simultaneously supply the fifth gate signal EM2 to two fifth gate lines GL5 of two pixel rows and may be sequentially supplied in the unit of two pixel rows.”)
Consider Claim 2:
No discloses the display panel of claim 1, wherein the pixel drive circuit comprises a data writing transistor, a drive transistor and a light emitting control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line to the drive transistor when a gate control signal provided by a scan line is effective; the drive transistor is configured to generate a drive current according to the data voltage; and the light emitting control transistor is configured to control the drive current generated by the drive transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is effective; (No, [0084], “The pixel circuit PC of the pixel PX1 may include first through eleventh transistors T1 to T11, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, a sixth gate line GL6, a driving voltage line PL, a reference voltage line VRL, and an initialization voltage line VIL.” See Fig. 4.)
the plurality of kinds of gate drive signals comprise a gate control signal for controlling the data writing transistor to turn on and off, and (No, [0088], “The second transistor T2 (a data writing transistor) may be connected between the data line DL and the first node N1. The second transistor T2 may be connected between the data line DL and the sixth node N6. The second transistor T2 may include a gate connected to the first gate line GL1, a first terminal connected to the data line DL, and a second terminal connected to the sixth node N6. The second transistor T2 may be turned on according to the first gate signal GW transmitted through the first gate line GL1 and may perform a switching operation of transmitting the data signal DATA transmitted to the data line DL to the sixth node N6.”)
a light emitting control signal for controlling the light emitting control transistor to turn on and off, and the plurality of kinds of gate drive signals are divided into two groups, wherein a first group of gate drive signals comprises the gate control signal, and a second group of gate drive signals comprises the light emitting control signal. (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 3:
No discloses the display panel of claim 2, wherein a high-level voltage of the first group of gate drive signals is greater than a high-level voltage of the second group of gate drive signals, and/or a low-level voltage of the first group of gate drive signals is greater than a low-level voltage of the second group of gate drive signals. (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 10:
No discloses a display apparatus, comprising the display panel of claim 1. (No, [0068], “The display apparatus 10 may include a display panel, and the display panel may include a substrate.)
Consider Claim 11:
No discloses a method for driving a display panel, comprising: (No, [0068], “The display apparatus 10 may include a display panel, and the display panel may include a substrate.)
controlling a plurality of kinds of gate drive circuits to output a plurality of kinds of gate drive signals to a plurality of transistors in a pixel drive circuit, (No, [0080], “In an embodiment, the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be respectively supplied to the first through sixth gate lines GL1 to GL6 of each pixel row at a certain timing. In another embodiment, the first gate signal GW may be sequentially supplied to the first gate line GL1 of each pixel row at a certain timing, and the second through sixth gate signals GI, GC, EM1, EM2, and GC2 may be sequentially and respectively supplied to second through sixth gate lines GL2 to GL6 of two pixel rows and may be sequentially supplied in the unit of two pixel rows. For example, the fifth gate driving circuit may simultaneously supply the fifth gate signal EM2 to two fifth gate lines GL5 of two pixel rows and may be sequentially supplied in the unit of two pixel rows.”)
wherein the plurality of kinds of gate drive signals are divided into at least two groups, high-level voltages of gate drive signals in a same group are the same, and low-level voltages of gate drive signals in a same group are the same; (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.”)
high-level voltages of gate drive signals in different groups are different, and/or low-level voltages of gate drive signals in different groups are different. (No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
Consider Claim 17:
No discloses the method for driving the display panel of claim 11, wherein the pixel drive circuit comprises a data writing transistor, a drive transistor and a light emitting control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line to the drive transistor when a gate control signal provided by a scan line is effective; the drive transistor is configured to generate a drive current according to the data voltage; and the light emitting control transistor is configured to control the drive current generated by the drive transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is effective; (No, [0084], “The pixel circuit PC of the pixel PX1 may include first through eleventh transistors T1 to T11, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, a sixth gate line GL6, a driving voltage line PL, a reference voltage line VRL, and an initialization voltage line VIL.” See Fig. 4.)
the plurality of kinds of gate drive signals comprise a gate control signal for controlling the data writing transistor to turn on and off, and (No, [0088], “The second transistor T2 (a data writing transistor) may be connected between the data line DL and the first node N1. The second transistor T2 may be connected between the data line DL and the sixth node N6. The second transistor T2 may include a gate connected to the first gate line GL1, a first terminal connected to the data line DL, and a second terminal connected to the sixth node N6. The second transistor T2 may be turned on according to the first gate signal GW transmitted through the first gate line GL1 and may perform a switching operation of transmitting the data signal DATA transmitted to the data line DL to the sixth node N6.”)
a light emitting control signal for controlling the light emitting control transistor to turn on and off; and the plurality of kinds of gate drive signals are divided into two groups, wherein a first group of gate drive signals comprises the gate control signal, and a second group of gate drive signals comprises the light emitting control signal. (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 18:
No discloses the method for driving the display panel of claim 17, wherein a high-level voltage of the first group of gate drive signals is greater than a high-level voltage of the second group of gate drive signals, and/or a low-level voltage of the first group of gate drive signals is greater than a low-level voltage of the second group of gate drive signals. (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over No et al. U.S. Patent Application Publication No. 2023/0368736 A1 as applied to claim 2, and 11 above, and further in view of Yang et al. U.S. Patent Application Publication No. 2008/0169754 A1 hereinafter Yang.
Consider Claim 4:
No discloses the display panel of claim 2, wherein the pixel drive circuit further comprises a reset transistor configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor, and a second electrode of the drive transistor; (No, [0083-0098], [0084], “The pixel circuit PC of the pixel PX1 may include first through eleventh transistors T1 to T11, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, a sixth gate line GL6, a driving voltage line PL, a reference voltage line VRL, and an initialization voltage line VIL.”)
wherein the plurality of kinds of gate drive signals comprise a reset control signal for controlling the reset transistor to turn on and off; (No, [0099-0112], [0099], “FIGS. 5 and 6 are schematic waveform diagrams for explaining an operation of a pixel according to an embodiment. FIG. 5 is a waveform diagram of signals applied to the pixel PX1 of FIG. 4 during a first scan period. FIG. 6 is a waveform diagram of signals applied to the pixel PX1 of FIG. 4 during a second scan period.”)
No however does not provide when the reset control signal and the gate control signal are correlated signals, the first group of gate drive signals comprises the reset control signal; and when the reset control signal and the gate control signal are uncorrelated signals, the second group of gate drive signals comprises the reset control signal.
Yang however teaches a pixel circuit wherein comprises a reset transistor configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor, and a second electrode of the drive transistor; (Yang, [0240-0248], [0241], “The pixel circuit has same configuration as that of FIG. 3, except for a light emitting control signal line (Em [n]), a first switching element (S1), a second switching element (S2), a third switching element (S3), a fourth switching element (S4), a fifth switching element (S5) and a sixth switching element (S6).” See Fig. 21.)
wherein the plurality of kinds of gate drive signals comprise a reset control signal for controlling the reset transistor to turn on and off; when the reset control signal and the gate control signal are correlated signals, the first group of gate drive signals comprises the reset control signal; and when the reset control signal and the gate control signal are uncorrelated signals, the second group of gate drive signals comprises the reset control signal. (Yang, [0250], “For the initializing period (T0), the fourth switching element (S4) is turned on when a scan signal of a low level is supplied from the prior scan line (Scan [n-1]). The fourth voltage is transferred to the control electrode of the first driving transistor (M1) by the turned-on fourth switching element (S4). The voltage for the control electrode of the first driving transistor (M1), i.e., the voltage stored in the first capacitive element (C1) is initialized.” and see [0251], “Next, a scan signal of the prior scan line (Scan [n-1]) is changed from a low level to a high level when a scan signal of a scan line (Scan [n]) is maintained at a high level for a delay period 1 (T2). If there is no delay period 1 (T2), the scan signal of the scan line (Scan [n]) is changed to a low level before the present data voltage is supplied, and the prior data voltage is supplied to the first driving transistor (M1) through the first switching element (S1).”)_
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a pixel circuit and timing as described in Yang as this was a known technique in the art and would have been utilized for the purpose of non-uniformity of the OLED is reduced. (Yang, [0257])
Consider Claim 19:
No discloses the method for driving the display panel of claim 17, wherein the pixel drive circuit further comprises a reset transistor configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor, and a second electrode of the drive transistor; (No, [0083-0098], [0084], “The pixel circuit PC of the pixel PX1 may include first through eleventh transistors T1 to T11, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, a sixth gate line GL6, a driving voltage line PL, a reference voltage line VRL, and an initialization voltage line VIL.”)
wherein the plurality of kinds of gate drive signals comprise a reset control signal for controlling the reset transistor to turn on and off; (No, [0099-0112], [0099], “FIGS. 5 and 6 are schematic waveform diagrams for explaining an operation of a pixel according to an embodiment. FIG. 5 is a waveform diagram of signals applied to the pixel PX1 of FIG. 4 during a first scan period. FIG. 6 is a waveform diagram of signals applied to the pixel PX1 of FIG. 4 during a second scan period.”)
No however does not provide when the reset control signal and the gate control signal are correlated signals, the first group of gate drive signals comprises the reset control signal; and when the reset control signal and the gate control signal are uncorrelated signals, the second group of gate drive signals comprises the reset control signal.
when the reset control signal and the gate control signal are correlated signals, the first group of gate drive signals comprises the reset control signal; and when the reset control signal and the gate control signal are uncorrelated signals, the second group of gate drive signals comprises the reset control signal. (Yang, [0240-0250], [0250], “For the initializing period (T0), the fourth switching element (S4) is turned on when a scan signal of a low level is supplied from the prior scan line (Scan [n-1]). The fourth voltage is transferred to the control electrode of the first driving transistor (M1) by the turned-on fourth switching element (S4). The voltage for the control electrode of the first driving transistor (M1), i.e., the voltage stored in the first capacitive element (C1) is initialized.” and see [0251], “Next, a scan signal of the prior scan line (Scan [n-1]) is changed from a low level to a high level when a scan signal of a scan line (Scan [n]) is maintained at a high level for a delay period 1 (T2). If there is no delay period 1 (T2), the scan signal of the scan line (Scan [n]) is changed to a low level before the present data voltage is supplied, and the prior data voltage is supplied to the first driving transistor (M1) through the first switching element (S1).”)_
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a pixel circuit and timing as described in Yang as this was a known technique in the art and would have been utilized for the purpose of non-uniformity of the OLED is reduced. (Yang, [0257])
Claim Rejections - 35 USC § 103
Claim(s) 5-9, 12-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over No et al. U.S. Patent Application Publication No. 2023/0368736 A1 as applied to claim 2 above, and further in view of Lin et al. U.S. Patent Application Publication No. 2020/0226978 A1 hereinafter Lin.
Consider Claim 5:
No discloses the display panel of claim 1, wherein the pixel drive circuit comprises a drive transistor, a data writing transistor, a reset transistor, a light emitting control transistor and a compensation transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line to the drive transistor when a first gate control signal provided by a first scan line is effective;
the drive transistor is configured to generate a drive current according to the data voltage; the light emitting control transistor is configured to control the drive current generated by the drive transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is effective;; and the compensation transistor is configured to perform threshold compensation on the drive transistor when a second gate control signal provided by a second scan line is effective; (No, [0083-0098], [0084], “The pixel circuit PC of the pixel PX1 may include first through eleventh transistors T1 to T11, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, a sixth gate line GL6, a driving voltage line PL, a reference voltage line VRL, and an initialization voltage line VIL.”)
the plurality of kinds of gate drive signals comprise a first gate control signal for controlling the data writing transistor to turn on and off, a second gate control signal for controlling the compensation transistor to turn on and off, a reset control signal for controlling the reset transistor to turn on and off, and a light emitting control signal for controlling the light emitting control transistor to turn on and off; the plurality of kinds of gate drive signals are divided into three groups, wherein a first group of gate drive signals comprises the first gate control signal, a second group of gate drive signals comprises the second gate control signal, and a third group of gate drive signals comprises the reset control signal and the light emitting control signal. (No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
No however does not specify the reset transistor is configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor and a second electrode of the drive transistor.
Lin however teaches a pixel circuit and driving where the reset transistor is configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor and a second electrode of the drive transistor. (Lin, [0124-0130], [0125], “FIG. 19B is a timing diagram illustrating the operation of pixel 22 shown in FIG. 19A. As shown in FIG. 19A, the operations prior to time t6 are performed during the active/refresh period, whereas the operations after time t6 are performed during the blanking period. At time t1, the emission signal EM may be deasserted (e.g., driven high) to begin the active period. During period Δt2, a pre-OBS/AR phase may be performed by selectively pulsing signal SC3(n). Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset for the OLED.” [0126], “During period Δt3, an initialization phase may be carried out by pulsing signal SC4 low while signal SC1 is high. Driving signal SC4 low will turn on p-channel silicon transistor Tini to apply initialization voltage Vini to the drain terminal of the drive transistor. Signal SC3 is high at this time, so no anode reset will be performed during Δt3.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the pixel circuit and driving method as this was a known technique in view of Lin and would have been utilized for the art recognized purpose to help compensate for any operational mismatch within pixel, thereby eliminating any residual flicker and closing any undesired luminance gaps when toggling between refresh and vertical blanking frames. (Lin, [0129])
Consider Claim 6:
No in view of Lin discloses the display panel of claim 5, wherein a high-level voltage of the first group of gate drive signals is greater than a high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the first group of gate drive signals is greater than a low-level voltage of the third group of gate drive signals; a high-level voltage of the second group of gate drive signals is less than the high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the second group of gate drive signals is less than the low-level voltage of the third group of gate drive signals. (Lin, [0124-0130], No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
Consider Claim 7:
No in view of Lin discloses the display panel of claim 6, wherein the high-level voltage of the first group of gate drive signals ranges from 9V to 10V, the high-level voltage of the second group of gate drive signals ranges from 6V to 7V, and the high-level voltage of the third group of gate drive signals ranges from 7.5V to 8.5V. (Lin, [0124-0130], No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
The Office notes that, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Consider Claim 8:
No in view of Lin discloses the display panel of claim 6, wherein the low-level voltage of the first group of gate drive signals ranges from -6V to -7V, the low-level voltage of the second group of gate drive signals ranges from -8V to -9V, and the low-level voltage of the third group of gate drive signals ranges from -7V to -8V. (Lin, [0124-0130], No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
The Office notes that, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Consider Claim 9:
No discloses the display panel of claim 1, wherein the pixel drive circuit comprises a drive transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light emitting control transistor and a compensation transistor, (No, [0084], [0086], “The first through ninth transistors T1 to T9 may be a P-type silicon thin-film transistor, and the tenth transistor T10 and the eleventh transistor T11 may be N-type oxide thin-film transistors. An on voltage of the gate signal for turning on the first through ninth transistors T1 to T9 may be a low level voltage (a second level voltage). An on voltage of the gate signal for turning on the tenth transistor T10 and the eleventh transistor T11 may be a high level voltage (a first level voltage).”)
wherein the data writing transistor is configured to write a data voltage provided by a data line to the drive transistor when a first gate control signal provided by a first scan line is effective; (No, [0088], “The second transistor T2 (a data writing transistor) may be connected between the data line DL and the first node N1. The second transistor T2 may be connected between the data line DL and the sixth node N6. The second transistor T2 may include a gate connected to the first gate line GL1, a first terminal connected to the data line DL, and a second terminal connected to the sixth node N6. The second transistor T2 may be turned on according to the first gate signal GW transmitted through the first gate line GL1 and may perform a switching operation of transmitting the data signal DATA transmitted to the data line DL to the sixth node N6.”)
the drive transistor is configured to generate a drive current according to the data voltage; (No, [0085], “The first transistor T1 may be a driving transistor in which the magnitude of a source-drain current is determined according to a gate-source voltage Vgs, and the second through eleventh transistors T2 to T11 may be switching transistors that are substantially turned on/off according to a gate voltage.”)
the light emitting control transistor is configured to control the drive current generated by the drive transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is effective; (No, [0087], “The first transistor T1 may be connected between the driving voltage line PL and the organic light-emitting diode OLED. The first transistor T1 may be connected to the driving voltage line PL via the fifth transistor T5 and may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6.”)
and the compensation transistor is configured to perform threshold compensation on the drive transistor when a second gate control signal provided by a second scan line is effective; (No, [0089], “The third transistor T3 (a compensation transistor) may be connected between the third node N3 and the fourth node N4. The third transistor T3 may be connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3 may include a gate connected to the third gate line GL3, a first terminal connected to the third node N3, and a second terminal connected to the fourth node N4.”)
the plurality of kinds of gate drive signals comprise a first gate control signal for controlling the data writing transistor to turn on and off, a second gate control signal for controlling the compensation transistor to turn on and off, a first reset control signal for controlling the first reset transistor to turn on and off, a second reset control signal for controlling the second reset transistor to turn on and off, and a light emitting control signal for controlling the light emitting control transistor to turn on and off; the plurality of kinds of gate drive signals are divided into five groups, wherein a first group comprises the first gate control signal, a second group comprises the second gate control signal, a third group comprises the first reset control signal, a fourth group comprises the second reset control signal, and a fifth group comprises the light emitting control signal. (No, [0075-0084], [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.”)
No however does not specify the first reset transistor is configured to reset a second electrode of the drive transistor when a first reset control signal is effective; the second reset transistor is configured to reset an anode of the light emitting element and a first electrode of the drive transistor when a second reset control signal is effective; and the compensation transistor is configured to perform threshold compensation on the drive transistor when a second gate control signal provided by a second scan line is effective.
Lin however discloses the exact pixel circuit wherein the first reset transistor is configured to reset a second electrode of the drive transistor when a first reset control signal is effective; (Lin, [0124-0130], [0126], “During period Δt3, an initialization phase may be carried out by pulsing signal SC4 low while signal SC1 is high. Driving signal SC4 low will turn on p-channel silicon transistor Tini to apply initialization voltage Vini to the drain terminal of the drive transistor. Signal SC3 is high at this time, so no anode reset will be performed during Δt3.”)
the second reset transistor is configured to reset an anode of the light emitting element and a first electrode of the drive transistor when a second reset control signal is effective; and (Lin, [0124-0130], [0125], “FIG. 19B is a timing diagram illustrating the operation of pixel 22 shown in FIG. 19A. As shown in FIG. 19A, the operations prior to time t6 are performed during the active/refresh period, whereas the operations after time t6 are performed during the blanking period. At time t1, the emission signal EM may be deasserted (e.g., driven high) to begin the active period. During period Δt2, a pre-OBS/AR phase may be performed by selectively pulsing signal SC3(n). Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset for the OLED.”)
the compensation transistor is configured to perform threshold compensation on the drive transistor when a second gate control signal provided by a second scan line is effective. (Lin, [0124-0130], [0126], “During period Δt3, an initialization phase may be carried out by pulsing signal SC4 low while signal SC1 is high. Driving signal SC4 low will turn on p-channel silicon transistor Tini to apply initialization voltage Vini to the drain terminal of the drive transistor. Signal SC3 is high at this time, so no anode reset will be performed during Δt3.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the pixel circuit and driving method as this was a known technique in view of Lin and would have been utilized for the art recognized purpose to help compensate for any operational mismatch within pixel, thereby eliminating any residual flicker and closing any undesired luminance gaps when toggling between refresh and vertical blanking frames. (Lin, [0129])
Consider Claim 12:
No in view of Lin discloses the display panel of claim 9, wherein a high-level voltage of the first group of gate drive signals is greater than a high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the first group of gate drive signals is greater than a low-level voltage of the third group of gate drive signals; a high-level voltage of the second group of gate drive signals is less than the high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the second group of gate drive signals is less than the low-level voltage of the third group of gate drive signals. (Lin, [0124-0130], No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 13:
No in view of Lin discloses the display panel of claim 9, wherein a high-level voltage of the fourth group of gate drive signals is equal to or approximately equal to the high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the fourth group of gate drive signals is equal to or approximately equal to the low-level voltage of the third group of gate drive signals. (Lin, [0124-0130], No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 14:
No in view of Lin discloses the display panel of claim 9, wherein a high-level voltage of the fifth group of gate drive signals is equal to or approximately equal to the high-level voltage of the third group of gate drive signals, and/or a low-level voltage of the fifth group of gate drive signals is equal to or approximately equal to the low-level voltage of the third group of gate drive signals. (No, [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.” See Fig. 5.)
Consider Claim 15:
No in view of Lin discloses the display panel of claim 9, wherein a high-level voltage of the first group of gate drive signals ranges from 9V to 10V, a high-level voltage of the second group of gate drive signals ranges from 6V to 7V, a high-level voltage of the third group of gate drive signals ranges from 7.5V to 8.5V, a high-level voltage of the fourth group of gate drive signals ranges from 7.5V to 8.5V, and a high-level voltage of the fifth group of gate drive signals ranges from 7.5V to 8.5V. (Lin, [0124-0130], No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
The Office notes that, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Consider Claim 16:
No in view of Lin discloses the display panel of claim 9, wherein a low-level voltage of the first group of gate drive signals ranges from -6V to -7V, a low-level voltage of the second group of gate drive signals ranges from -8V to -9V, a low-level voltage of the third group of gate drive signals ranges from -7V to -8V, a low-level voltage of the fourth group of gate drive signals ranges from -7V to -8V, and a low-level voltage of the fifth group of gate drive signals ranges from -7V to -8V. (Lin, [0124-0130], No, [0099-0112], [0101], “The gate driving circuit 130A may supply first through sixth gate signals GW, GC, EM1, EM2, and GC2 to first through sixth gate lines GL1, GL2, GL3, GL4, GL5, and GL6, respectively. Start timings and ending timings of an on voltage maintenance period and an off voltage maintenance period of the first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 may be the same or different from each other, and some signals may overlap each other in some periods.”)
The Office notes that, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Consider Claim 20:
No discloses the method for driving the display panel of claim 11, wherein the pixel drive circuit comprises a drive transistor, a data writing transistor, a reset transistor, a light emitting control transistor and a compensation transistor, (No, [0084], [0086], “The first through ninth transistors T1 to T9 may be a P-type silicon thin-film transistor, and the tenth transistor T10 and the eleventh transistor T11 may be N-type oxide thin-film transistors. An on voltage of the gate signal for turning on the first through ninth transistors T1 to T9 may be a low level voltage (a second level voltage). An on voltage of the gate signal for turning on the tenth transistor T10 and the eleventh transistor T11 may be a high level voltage (a first level voltage).”)
wherein the data writing transistor is configured to write a data voltage provided by a data line to the drive transistor when a first gate control signal provided by a first scan line is effective; (No, [0088], “The second transistor T2 (a data writing transistor) may be connected between the data line DL and the first node N1. The second transistor T2 may be connected between the data line DL and the sixth node N6. The second transistor T2 may include a gate connected to the first gate line GL1, a first terminal connected to the data line DL, and a second terminal connected to the sixth node N6. The second transistor T2 may be turned on according to the first gate signal GW transmitted through the first gate line GL1 and may perform a switching operation of transmitting the data signal DATA transmitted to the data line DL to the sixth node N6.”)
the drive transistor is configured to generate a drive current according to the data voltage; (No, [0085], “The first transistor T1 may be a driving transistor in which the magnitude of a source-drain current is determined according to a gate-source voltage Vgs, and the second through eleventh transistors T2 to T11 may be switching transistors that are substantially turned on/off according to a gate voltage.”)
the light emitting control transistor is configured to control the drive current generated by the drive transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emitting control signal provided by a light emitting line is effective; (No, [0087], “The first transistor T1 may be connected between the driving voltage line PL and the organic light-emitting diode OLED. The first transistor T1 may be connected to the driving voltage line PL via the fifth transistor T5 and may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6.”)
the compensation transistor is configured to perform threshold compensation on the drive transistor when a second gate control signal provided by a second scan line is effective; (No, [0089], “The third transistor T3 (a compensation transistor) may be connected between the third node N3 and the fourth node N4. The third transistor T3 may be connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3 may include a gate connected to the third gate line GL3, a first terminal connected to the third node N3, and a second terminal connected to the fourth node N4.”)
the plurality of kinds of gate drive signals comprise a first gate control signal for controlling the data writing transistor to turn on and off, a second gate control signal for controlling the compensation transistor to turn on and off, a reset control signal for controlling the reset transistor to turn on and off, and a light emitting control signal for controlling the light emitting control transistor to turn on and off; the plurality of kinds of gate drive signals are divided into three groups, wherein a first group of gate drive signals comprises the first gate control signal, a second group of gate drive signals comprises the second gate control signal, and a third group of gate drive signals comprises the reset control signal and the light emitting control signal. (No, [0075-0084], [0078], “The gate driving circuit 130A may be connected to the first through sixth gate lines GL1 to GL6 and may sequentially supply first through sixth gate signals GW, GI, GC, EM1, EM2, and GC2 to the first through sixth gate lines GL1 to GL6, respectively. The gate driving circuit 130A may include first through fifth gate driving circuits. Each of the first through fifth gate driving circuits may include multiple stages.”)
No however does not suggest that the reset transistor is configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor and a second electrode of the drive transistor.
Lin however discloses the exact pixel circuit and the reset transistor is configured to, when a reset control signal is effective, reset at least one of: an anode of the light emitting element, a first electrode of the drive transistor and a second electrode of the drive transistor. (Lin, [0124-0130], [0125], “FIG. 19B is a timing diagram illustrating the operation of pixel 22 shown in FIG. 19A. As shown in FIG. 19A, the operations prior to time t6 are performed during the active/refresh period, whereas the operations after time t6 are performed during the blanking period. At time t1, the emission signal EM may be deasserted (e.g., driven high) to begin the active period. During period Δt2, a pre-OBS/AR phase may be performed by selectively pulsing signal SC3(n). Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset for the OLED.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the pixel circuit and driving method as this was a known technique in view of Lin and would have been utilized for the art recognized purpose to help compensate for any operational mismatch within pixel, thereby eliminating any residual flicker and closing any undesired luminance gaps when toggling between refresh and vertical blanking frames. (Lin, [0129])
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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