DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph, standalone on a separate sheet of paper, within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a1)/(a2) as being anticipated by Akkary et al. (US 2005/0120179).
Regarding claim 1, Akkari et al. discloses a method performed on a processor using a hierarchical store queue [FIG. 1, ¶0017: a hierarchical store queue], the method comprising: receiving a load instruction having an address corresponding to an entry in the hierarchical store queue [¶0003, 0032: the store queues serve three functions: disambiguating memory addresses, buffering stores until retirement, and forwarding data to dependent load operations; the L2 stores store-distances indexed by the load instruction address]; performing a hierarchical search to find the entry in the hierarchical store queue, wherein performing the hierarchical search comprises searching a first partition of the hierarchical store queue for the entry before searching a second partition of the hierarchical store queue [FIG. 5A, 5B, ¶0027, 0030: when a load is used and while the L2 CT is being read, the L1 STQ may be accessed in parallel, if the load hits the L1 STQ, the store data may not be forwarded to the load, if the load misses the L1 STQ, and the L2 CT does not have matching address, the data may be forwarded to the load, storing a previous store to a second level circuit, allocating entry at a tail of a first level store queue, determining a previous store in the first level store queue, first level store queue, second level circuit including an address matching circuit]; and reading a value of the entry from the hierarchical store queue for the load instruction [¶0030: when a load is issued and while the L2 CT is being read the L1 STQ may be accessed].
Regarding claim 2, Akkari et al. discloses the method of claim 1, wherein the first partition is smaller than the second partition [FIGs. 1-2].
Regarding claim 3, Akkari et al. discloses the method of claim 1, further comprising: performing a store-to-load forwarding process for the load instruction [¶0003: store-to-load forward].
Regarding claim 4, Akkari et al. discloses the method of claim 1, wherein the hierarchical store queue is a circular queue partitioned logically using a pointer that denotes a first entry to search in the first partition [¶0016, 0026; Claim 13: circular buffer with head and tail pointers].
Regarding claim 5, Akkari et al. discloses the method of claim 4, wherein the pointer that denotes the first entry in the first partition is located at an offset from a tail pointer representing a most recently added entry in the hierarchical store queue [¶0016, 0028; Claim 19: circular buffer with head and tail pointers].
Regarding claim 6, Akkari et al. discloses the method of claim 5, wherein performing the hierarchical search comprises: determining that the entry is not located in the first partition [¶0037, 0038]; and in response, searching the second partition from a location indicated by a head pointer, the head pointer representing the oldest entry in the hierarchical store queue [¶0037; Claims: 2].
Regarding claim 7, Akkari et al. discloses the method of claim 6, wherein the first partition ranges from the tail pointer to the pointer that denotes the first entry, and the second partition ranges from the pointer that denotes the first entry to the head pointer [¶0038, Claim 2].
Regarding claim 8, Akkari et al. discloses the method of claim 5, wherein the offset is a store-to-load window of the store-to-load forwarding process [Claim 14].
Regarding claim 9, Akkari et al. discloses the method of claim 8, wherein a size of the store-to-load window is global to the processor or local to the load instruction of the store-to-load forwarding process [Claim 20].
Regarding claim 10, Akkari et al. discloses the method of claim 6, further comprising: receiving a store instruction to store a value in the hierarchical store queue [¶0018]; determining to retire an entry from the hierarchical store queue to a store gather buffer [Claim 11, 17]; retiring the entry to the store gather buffer in a first-in first-out manner, wherein the entry is the oldest entry indicated by the head pointer [¶0018, 0027]; and writing the value from the store instruction in the hierarchical store queue [¶0018].
Regarding claim 11, Akkari et al. discloses the method of claim 11, wherein the hierarchical store queue is partitioned physically using separate hierarchical store queue devices [FIG. 5: an instruction window 552, a first level store queue 554, first level store queue 558].
Regarding claim 12, Akkari et al. discloses the method of claim 11, wherein performing the hierarchical search comprises: determining that the entry is not located in the first partition [¶0037, 0038]; and in response, searching a second device implementing the second partition [¶0037; Claims: 2].
Regarding claim 13, Akkari et al. discloses the method of claim 12, wherein the first partition ranges from a first tail pointer to a first head pointer and the second partition ranges from a second tail pointer to a second head pointer, wherein the first tail pointer and the second tail pointer indicate the most recent entry in the respective partition, and the first head pointer and the second head pointer indicate the oldest entry in the respective partition [¶0016, 0028].
Regarding claim 14, Akkari et al. discloses the method of claim 11, wherein performing the store-to-load forwarding process at the second partition is at least one cycle slower than performing the store-to-load forwarding process at the first partition [¶0029, Claim 14, 20].
Regarding claim 15, Akkari et al. discloses the method of claim 11, further comprising: receiving a store instruction to store a value in the hierarchical store queue [¶0018]; determining whether to retire an entry of the hierarchical store queue to a store gather buffer by determining whether the first partition and the second partition are full [¶0003, 0032: the store queues serve three functions: disambiguating memory addresses, buffering stores until retirement, and forwarding data to dependent load operations; the L2 stores store-distances indexed by the load instruction address]; and writing the value of the store instruction to the first partition or the second partition based on determining whether the first partition and the second partition are full [FIG. 5B].
Regarding claim 16, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 17, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 18, the rationale in the rejection of claim 2 is herein incorporated.
Regarding claim 19, the rationale in the rejection of claim 3 is herein incorporated.
Regarding claim 20, the rationale in the rejection of claim 4 is herein incorporated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. AVUDAIYAPPAN et al. (US20170199822) discloses systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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