N O N - F I N A L A C T I O N
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/05/25 complies with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Closest Prior Art
The prior art (cited on PTO-892) is considered pertinent to applicant's disclosure. Among these, the following references are considered to be the closest, collectively disclosing the state of the art concerned with a digital camera configured with an image sensor having a stacked chip architecture having pixel array circuitry, ADC circuitry, DAC circuitry, and test circuitry.
OKA (EP-3748955-A1) – applied to 35 USC 102/103 rejection, (English translation attached), see Abstract, Fig. 4, Fig. 18-19, Fig. 32, and para [0188-221 & 0313-340].
OKA (US 20190297287) – (this reference corresponds EP-3748955-A1), see Abstract, Fig. 4, Fig. 18-19, Fig. 32, and para [0268-302 & 0401-431].
IWANE (US 20210289195) – applied to 35 USC 103 rejection, see Abstract, Fig. 6, and para [0074].
KAWAZU (US 20220279121) – see Abstract, Fig. 4, Fig. 14, and para [0085-87 & 0125-126].
NOTE: Examiner welcomes INTERVIEW(s) to discuss the instant application’s claimed invention as it corresponds to the specification embodiments, as well as, discussing the similarities/differences taught/not taught by prior art. In the interest of compact prosecution, Applicant’s arguments/amendments should not only address the cited closest art applied/relied on in the 35 USC 102/103 rejection (below), but also address the other cited closest art not applied/relied on.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections – 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 9, and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OKA (EP-3748955-A1) -- hereafter, termed as shown “underlined”.
As per INDEPENDENT CLAIM 1, OKA teaches a circuit chip (Fig. 4 in view of Fig. 18-19, see para [0191] discussion for a lower chip 91), comprising:
a first circuit chip contact area configured to be electrically connected to a first pixel chip contact area of a pixel chip (first circuit chip contact area - see para [0191] discusses a TCV 93);
a first signal line electrically (see para [0191] discusses a vertical transfer line VSL) connected to the first circuit chip contact area (see para [0191] discusses VSL connected via TCV 93);
a first comparator circuit (see para [0201] discusses ADC 242 includes a comparator 261), wherein the first signal line is electrically coupled to a first input of the first comparator circuit (see para [0202] discusses comparator 261 performs a comparison between a ramp voltage (Ramp) that is supplied from the DAC 263 and varies at predetermined step intervals in synchronism with a clock from the counter 262, and a pixel signal formed with the analog signal input from the load MOS 241);
a first test circuit comprising (see para [0206] discusses ADC+TVC failure detector 271 controls the DSF circuit 250) a digital-to-analog converter circuit, the first test circuit being configured to output a test signal (see DAC and para [0206] discussion for a predetermined pixel signal) at an output of the first test circuit (see para [0196] discusses transistor 252 is a transistor for supplying the vertical transfer line VSL with a dummy pixel signal that is formed with a fixed signal);
and a first switching element (see para [0196] discussion for switch transistor 251) electrically coupled in series between the output of the first test circuit and the first signal line (see para [0196] discusses the switch transistor 251 switches between outputting a pixel signal from the selection transistor 235 to the vertical transfer line VSL and outputting a dummy pixel signal from the DSF transistor 252 to the vertical transfer line VSL).
As per CLAIM 2, OKA teaches the circuit chip of claim 1, wherein the first switching element is operable to switch between electrically connecting the output of the first test circuit and the first signal line and electrically disconnecting the output of the first test circuit and the first signal line based on a first switching element input signal (Fig. 18-19, see discussion in para [0196]: The switch transistor 251 switches between outputting a pixel signal from the selection transistor 235 to the vertical transfer line VSL and outputting a dummy pixel signal from the DSF transistor 252 to the vertical transfer line VSL).
As per CLAIM 3, OKA teaches the circuit chip of claim 1, further comprising a test control circuit (Fig. 18-19, see discussion in para [0206]: ADC + TVC failure detector 271 controls the DSF circuit) configured to generate and output the first switching element input signal to a control input of the first switching element, and wherein the test control circuit is further configured to generate and output a binary test signal to the digital-to-analog converter circuit of the first test circuit (Fig. 18-19, see discussion in para [0206]: The ADC + TVC failure detector 271 controls the DSF circuit 250 to output a dummy pixel signal during a blanking period or the like, for example, and compares the pixel signal converted to a digital signal by the ADC 242 with a predetermined pixel signal that is set as the dummy pixel signal in advance).
As per CLAIM 5, OKA teaches the circuit chip of claim 1, further comprising: a voltage ramp generator circuit (Fig. 18-19, see DAC 263 / 263-1 as discussed in para [0210]) comprising a second digital-to-analog converter circuit, wherein an output (a ramp voltage per para [0210]) of the voltage ramp generator circuit is electrically connected to a second input of the first comparator circuit (Fig. 18-19, see comparators 261-1 as discussed in para [0210]).
As per CLAIM 9, OKA teaches the circuit chip of claim 1, further comprising: a second circuit chip contact area (para [0209]: TCVs also include 93-12) configured to be electrically connected to a second pixel chip contact area of the pixel chip; a second signal line electrically (Fig. 19: 281-2) connected to the second circuit chip contact area; a second comparator circuit (para [0210]: see comparators 261-1 includes second comparator), wherein the second signal line (para [0208]: column signal line 281-2) is electrically coupled to a first input of the second comparator circuit; a second test circuit (para [0209]: 250-2-2) comprising an output (Fig. 19: 281-2); and a second switching element electrically coupled in series between the output of the second test circuit and the second signal line (Fig. 18-19, see discussion in para [0196 & 0209]: second test circuit 250-2-2 with output 281-2 and second switching element 251).
As per CLAIM 11, OKA teaches the circuit chip of claim 1, further comprising a third test circuit comprising a resistive divider circuit, the third test circuit being configured to output a test signal at an output of the third test circuit (These features describe a conventional voltage generation circuit for generating the voltages which are considered anticipated over OKA’s teachings concerning potential V1 and potential V2 per para [0221]).
As per CLAIM 12, OKA teaches the circuit chip of claim 11, further comprising a switch array circuit electrically coupled in series between the output of the third test circuit and the first switching element (Fig. 18-19, see para [0197] discusses a plurality of DSF transistors 252 may be provided to output a plurality of pixel signals formed with predetermined pixel values in a switching manner).
As per CLAIM 13, OKA teaches the solid-state imaging device (Fig. 18: imaging device 72, para [0188]), comprising:
the circuit chip of claim 1 (see claim 1; and para [0191] discussion for lower chip 91);
and the pixel chip stacked over the circuit chip (Fig. 4 in view of para [0191] discussion for upper chip 92), wherein the pixel chip includes a plurality of pixel circuits arranged in a matrix pattern, and a first vertical signal line (see para [0192] discusses the pixel circuit forming each of the pixels arranged in an array in the above described pixel array 101), wherein a group of the plurality of pixel circuits is electrically coupled to the first vertical signal line, and the first vertical signal is electrically connected to the first signal line of the circuit chip via the first pixel chip contact area and the first circuit chip contact area (Fig. 4 in view of Fig. 18-19 with discussion in para [0191] states the vertical transfer line VSL is provided with a DSF circuit 250 that includes a switch transistor 251 and a DSF transistor 252. Note that the DSF circuit 250 including the switch transistor 251 and the DSF transistor 252 is not disposed in the pixel array 101 in the upper chip 92 but is disposed in the lower chip 91, and is connected to the vertical transfer line VSL via a TCV 93).
As per CLAIM 14, OKA teaches the solid-state imaging device of claim 13, wherein the pixel chip is stacked directly on the circuit chip (Fig. 4 and Fig. 19 in view of para [0313] states the upper chip 92 as the first chip and the lower chip 91 as the second chip stacked under the upper chip 92 are electrically connected by the TCVs 93-1, 93-2, 93-11, and 93-12).
As per CLAIM 15, OKA teaches the solid-state imaging device of claim 13, further comprising at least one chip arranged between the pixel chip and the circuit chip (See three stacked chips in Fig. 32 in view of para [0323] shows / discusses a floor plan in which the imaging device 72 and the front camera ECU 73 are formed by stacking a first layer chip 501, a second layer chip 502, and a third layer chip 503 in this order from the top. Further, see discussion in para [0340] stating the failure detector 521 may also be provided in the third layer chip 503).
Claim Rejections – 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over OKA (EP-3748955-A1) in view of IWANE (US 20210289195) -- hereafter, termed as shown “underlined”.
As per CLAIM 4, OKA teaches the circuit chip of claim 1. Regarding the limitations: “a first test chip contact area electrically coupled to a control input of the first switching element, and a second test chip contact area electrically coupled to the digital-to-analog converter circuit of the first test circuit”, these features are not explicitly taught by OKA, however, these features for providing test signals outside from the circuit chip are well known in the field of chip testing.
For example, see prior art IWANE, Fig. 6 in view of para [0074] discloses…on the second substrate 102, the vertical scanning circuit 120, the control circuit 130, the voltage potential output unit 140 and the image signal output unit 150 are arranged. That is, the circuit between the node NL and the pad electrode 142 (second circuit) is disposed on the second substrate, and the circuit between node NL and the pad electrode 156 (first circuit) is also disposed on the second substrate.
Thus, when considering the collective knowledge bestowed by each applied prior art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to COMBINE the teachings of IWANE into suitable modification with the teachings of OKA to produce Applicant’s claimed invention with the structural arrangement / functional configuration stated in said underlined limitation for the MOTIVATED REASON of improving detection sensitivity of incident light in the analogous art of a digital camera.
Claims 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over OKA (EP-3748955-A1) -- hereafter, termed as shown “underlined”.
As per CLAIM 6, OKA teaches the circuit chip of claim 5. Regarding the limitation: “wherein more than 80% of a layout of the second digital-to-analog converter circuit is reused in the digital-to-analog converter circuit of the first test circuit”, these features define at most that the first and second digital-to-analog converter circuit share some elements, which is a common practice for generating predetermined voltages. Such a ratio lacks novelty because the size of these areas depends merely on the design requirements. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as a matter of design choice to configure more than 80% of a layout of the second digital-to-analog converter circuit is reused in the digital-to-analog converter circuit of the first test circuit, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
As per CLAIM 7, OKA teaches the circuit chip claim 5. Regarding the limitation: “wherein the digital-to-analog converter circuit of the first test circuit is an n-bit digital-to-analog converter circuit, n ranging from 6 to 14”, these features define an arbitrary number of bit depth, which is defined only by the required precision of ADC testing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an n-bit digital-to-analog converter circuit with n ranging from 6 to 14, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
As per CLAIM 8, OKA teaches the circuit chip of claim 7. Regarding the limitation: “wherein a layout area of the digital-to-analog converter circuit of the first test circuit ranges from 5% to 20% of a layout area of the second digital-to-analog converter circuit”, these features define an arbitrary relation or ratio between areas of different circuits. Such a ratio lacks novelty because the size of these areas depends merely on the design requirements. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as a matter of design choice to configure the layout area of the digital-to-analog converter circuit of the first test circuit to a smaller layout area (i.e. ranging from 5% to 20% smaller), since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
As per CLAIM 10, OKA teaches the circuit chip of claim 9, further comprising a first number of circuit chip contact areas laterally arranged between the first chip contact area and the second chip contact area (These features are met over para [0209] which states DSF circuits 250-1 (250-1-1, 250-1-2, . . . ) are provided in the lower chip 91-1, and supply a dummy pixel signal to ADCs 242-2 (242-2-1, 242-2-2, . . . ) of the other lower chip 91-2 via the TCVs 93-11 and 93-12 and the pixel array 101. Likewise, DSF circuits 250-2 (250-2-1, 250-2-2, . . . ) are provided in the lower chip 91-2).
Regarding the limitation: “wherein the first number ranges from ⅛ of a total number of the signal lines to the total number of the signal lines, wherein each of the first number of circuit chip contact areas is electrically coupled to the first test circuit”, these features define an arbitrary partitioning / size of the circuit chip contact areas.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as a matter of design choice to use a range from ⅛ of a total number of the signal lines to the total number of the signal lines, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Contact Information
Any inquiry concerning this communication or earlier communications from the EXAMINER should be directed to AKSHAY TREHAN whose telephone number is (571) 270-5252. The examiner can normally be reached between the hours of 10am – 6pm during the weekdays Monday – Friday.
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/AKSHAY TREHAN/
Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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