Prosecution Insights
Last updated: October 02, 2026
Application No. 19/165,129

METHOD FOR CONTROLLING DIRECTION OF DATA STREAM, AND DIMMER AND BACKLIGHT UNIT

Non-Final OA §103
Filed
Sep 14, 2025
Priority
Mar 15, 2023 — CN 202310250806.5 +1 more
Examiner
NGUYEN, JIMMY H
Art Unit
2626
Tech Center
2600 — Communications
Assignee
BEIJING XIANXIN TECHNOLOGY CO., LTD
OA Round
1 (Non-Final)
58%
Grant Probability
Moderate
1-2
OA Rounds
2y 3m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
393 granted / 676 resolved
-3.9% vs TC avg
Strong +32% interview lift
Without
With
+32.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
24 currently pending
Career history
709
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
37.7%
-2.3% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
31.6%
-8.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 676 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is made in response to applicant’s preliminary amendment filed on 09/14/2025. Claims 1-5 and 11-25 are currently pending in the application. An action follows below: Claim Objections Claims 1-3, 11, 15, 16, 19, 21, 24 and 25 are objected to because of the following informalities: -- bidirectional -- should be inserted immediately before “input/output” in order to clarify the term so as to be consistent with paragraph [0056] of the specification. Appropriate correction is required. Note that since the specification is not the measure of invention, limitation(s) contained therein can’t be read into the claim(s). See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968). If the claims are not appropriately corrected, the term, “input/output pin,” typically means “input pin or output pin,” based on the plain meaning of the term. Notice to Applicant(s) Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968). Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims. Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 11-25 are rejected under 35 U.S.C. 103 as being unpatentable over Beijing Xingeno Microelectronics CO LTD (CN114974140 A; hereinafter Beijing; see the attached Machined English Translation for the following citations) in view of Luo (US 2021/0288580 A1.) As per claim 1, Beijing discloses a method for controlling a direction of data stream, performed by a backlight unit, wherein the backlight unit comprises a dimmer (see at least Figs. 5-6; pages 1-2 of the translation, disclosing a backlight module/plate/unit comprising a plurality of LED driver chips, each corresponding to the claimed dimmer, and a method for controlling a direction of data stream transmitted form the host, performed by a backlight unit,) the method comprises: receiving, by the dimmer, input signals through input/output pins, and detecting by the dimmer, level states of the input signals (see at least Figs. 2-6 and pages 1-2 of translation, disclosing each LED driver chip [as the dimmer] comprising a master controller 1, a first input/output port 2, a first port detection circuit 3, a second input/output port 4, and a second port detection circuit 5. The first input/output port 2 and the second input/output port 4 (equivalent to input/output pins) are not designated as a fixed input port or a fixed output port, and instead, but are adaptively configured as an input port or an output port on the basis of a change in a level signal detected by the ports. When the level of one of the first input/output port 2 and the second input/output port 4 is detected to be lower or higher (equivalent to on the basis of a detected level state), i.e., it is considered that there is an input signal, the input/output port is defined as an input port (equivalent to selecting an input/output pin as an input pin), and data is received from the port (equivalent to receiving an input signal); meanwhile, the other one of the first input/output port 2 and the second input/output port 4 is defined as an output port (equivalent to the other input/output pin other than the input pin being used as an output pin), data needing to be sent is sent to the other input/output port (equivalent to transmitting dimming data from the input pin to the output pin), and the other input/output port outputs the data to a subsequent LED driver chip;) selecting, by the dimmer, an input/output pin from two input/output pins of the dimmer as an input pin based on the detected level states see the above discussion;) and using, by the dimmer, another input/output pin other than the input pin as an output pin, to cause that dimming data is transmitted from the input pin to the output pin (see the above discussion.) Accordingly, Beijing discloses all limitations of this claim except for “selecting a pin as an input pin on the basis of a first preset time length,” as claimed. However, a technique for preventing false determination due to false triggering caused by a level change in a short time, when determining a level state, the determination being considered to be valid only after lasting for a predetermined duration is well-known and expected in the art. Luo teaches a technique for preventing false determination due to false triggering caused by a level change in a short time, when determining a level state, the determination being considered to be valid only after lasting for a preset time period [as the predetermined duration] (see at least Figs. 8-10 and the corresponding description at least ¶ 84.) Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to use the above-discussed technique, in the method of Beijing, so as to render the step of selecting, by the dimmer, an input/output pin from two input/output pins of the dimmer as an input pin based on the detected level states and based on a first preset time length, in view of the teaching in the Luo reference, to improve the above modified method of the Beijing reference for the predictable result of preventing false determination due to false triggering caused by a level change in a short time. As per claim 2, Beijing in view of Luo obviously renders: discloses: wherein the selecting, by the dimmer, an input/output pin from two input/output pins of the dimmer as an input pin based on the detected level states and based on a first preset time length (see the rejection of claim 1) comprises: using, by the dimmer, the input/output pin through which an input signal with the detected level state being a preset level state is provided and lasts for the first preset time length at the input/output pin as the input pin (Beijing, as discussed in the rejection of claim 1, disclosing: using, by the dimmer, the input/output pin through which an input signal with the detected level state at the input/output pin as the input pin; Luo, at least Figs. 8-10 and the corresponding description at least ¶ 84, disclosing: an input signal with the detected level state being a preset level state is provided and lasts for the first preset time period.) As per claim 3, Beijing in view of Luo obviously renders: wherein in response to that the level states detected by the dimmer are the preset level state, and the input/output pins through which the input signals with the preset level state are provided and lasts for the first preset time length at the input/output pins comprise the two input/output pins, the method further comprises: determining, by the dimmer, an input/output pin that receives an input signal in the preset level state earlier from the two input/output pins; and using, by the dimmer, the determined input/output pin as the input pin (Beijing in view of Luo obviously renders these limitations by repeating for the second input/output pin, as discussed in the rejections of claims 1-2.) As per claim 4, Beijing in view of Luo obviously renders: wherein in response to that the backlight unit comprises at least one group of cascaded dimmers (see Beijing at least Figs. 2, 5, 6, disclosing the backlight unit comprises at least one group of cascaded dimmers), for each dimmer in each group of cascaded dimmers, the method further comprises: receiving, by the dimmer, an input signal in a preset level state through the input pin within a second preset time length, and outputting, by the dimmer, a signal in the preset level state to a next-level dimmer connected to the dimmer through the output pin within a third preset time length; wherein the third preset time length is a product of the first preset time length and a quantity of subsequent-level dimmers of the dimmer, and the second preset time length is a sum of the third preset time length and the first preset time length (see Luo at least Figs. 1-3, 8-10 and the corresponding description at least ¶ 84, disclosing: in a group of cascaded circuits [101-10N], a first circuit 101 receiving an input signal in a preset level state through the input pin/terminal within a second preset time period/length (e.g., Tpre0), and outputting, by the first circuit, a signal in the preset level state to a next-level circuit connected to the first circuit through the output pin within a third preset time period/length; wherein the third preset time length is a product of the first preset time length and a quantity of subsequent-level circuits of the first circuit, and the second preset time period/length is a sum of the third preset time length and the first preset time length; therefore, Beijing in view of Luo obviously renders these limitations. In the alternative, since Beijing, at least Figs. 2, 5, 6, discloses the backlight unit comprising at least one group of cascaded dimmers and Beijing in view of Luo, as discussed in the rejection of claims 1-3, obviously renders a first dimmer receiving an input signal in a preset level state through the input pin within a second preset time period/length, and outputting a signal in the preset level state to a next-level dimmer connected to the dimmer through the output pin within a third preset time period/length; wherein the third preset time period/length is a product of the first preset time period/length and a quantity of subsequent-level dimmers of the first dimmer, and the second preset time period/length is a sum of the third preset time period/length and the first preset time period/length.) As per claim 5, Beijing in view of Luo obviously renders: the method further comprising: in response to that a preset condition is met, setting, by the dimmer, the two input/output pins of the dimmer as input pins; wherein the preset condition is any one of following conditions: condition 1: the dimmer is reset; condition 2: the backlight unit is powered on; or condition 3: the backlight unit is powered off (see Beijing at least page 2 of translation.) . As per claim 13, Beijing in view of Luo obviously renders: wherein the preset level state is a constant high level state or a constant low level state (see Beijing at least page 2:28-34 of translation.) As per claim 14, Beijing in view of Luo obviously renders: the method further comprising: receiving, by the dimmer, the dimming data as the input signals from a dimmer controller (see Beijing at least Figs. 2-4, page 1 of the translation, disclosing the LED driver chip [the dimmer] receiving the dimming data as the input signals from a main controller 1 as the dimmer controller.) As per claim 15, Beijing in view of Luo obviously renders: each input/output pin is a bidirectional input/output pin (see Beijing at least page 2:25-26 of the translation “… both ports … are bidirectional IO ports …”.) As per claim 16, Beijing in view of Luo obviously renders: wherein the dimmer is provided with a positioning hole, an input/output pin of the dimmer distal to the positioning hole is electrically connected to one terminal of the first resistor, and another input/output pin of the dimmer close to the positioning hole is electrically connected to one terminal of the second resistor, and another terminal of the first resistor and another terminal of the second resistor are both grounded (see Beijing at least Figs. 2-6.) As per claim 17, Beijing in view of Luo obviously renders: wherein an output pin of a last-level dimmer of the at least one group of cascaded dimmers is floating (see Beijing at least Fig. 2; page 2 of the translation, disclosing an output pin of a last-level dimmer of the at least one group of cascaded dimmers is in high resistance output state, i.e., in floating state.) As per claim 11, Beijing discloses the dimmers applied to the backlight unit (see the discussion in the rejection of claim 1; or see at least Figs. 5-6; pages 1-2 of the translation, disclosing a backlight module/plate/unit comprising a plurality of LED driver chips, each corresponding to the claimed dimmer.) Moreover, Official Notice is taken that both the concept and the advantages of providing each dimmer comprising a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of a control method are well-known and expected in the art. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to modify the dimmer of Beijing to include a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of a control method, to obtain the same predictable result. Further, see the rejection of claim 1 for similar steps/operations in last 6 lines of this claim. Accordingly, the above modified Beijing obviously renders all limitations of this claim. As per claim 12, Beijing further discloses that the backlight unit comprises the Mini LEDs and the LED driver chips as the dimmers (see the discussion in the rejection of claim 1 or see Beijing at least Figs. 2-3.) Moreover, a person of ordinary skill in the art would have readily recognized that a dimmer is used for adjusting, on the basis of dimming data, the brightness of a Mini LED connected to the dimmer. As per claims 18-25, see the rejections of claims 2-5 and 13-16 for similar limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jimmy H Nguyen/ Primary Examiner, Art Unit 2626
Read full office action

Prosecution Timeline

Sep 14, 2025
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103
Sep 23, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
58%
Grant Probability
90%
With Interview (+32.4%)
3y 4m (~2y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 676 resolved cases by this examiner. Grant probability derived from career allowance rate.

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