DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is made in response to applicant’s preliminary amendment filed on 09/17/2025. Claims 1-10 are currently pending in the application. An action follows below:
Notice to Applicant(s)
A person skilled in the display or relevant art would have readily recognized that, in light of Fig. 3 and the corresponding specification, [[image]] data output[ted] from the data transmission unit 210 of the timing controller to the impedance matching circuit 221, data output[ted] from the impedance matching circuit 221 to the equalizer circuit 222, data output[ted] from the equalizer circuit 222 to the CDR unit 230, data output[ted] from the CDR unit 230 to the data alignment unit 240, and data output[ted] from the data alignment unit 240 to the display panel are different from each other due to at least the operations and the processing delayed times of these circuits [221, 222] and units [230, 240]. Therefore, the above-discussed must be designated with different names, e.g., data output[ted] from the impedance matching circuit 221 replaced with “impedance matching [[image]] data”, data output[ted] from the equalizer circuit 222 replaced with “equalized [[image]] data”, data output[ted] from the CDR unit 230 replaced with “recovered [[image]] data”, and data output[ted] from the data alignment unit 240 replaced with “aligned [[image]] data”. Note that, if the Applicant does not appropriately amend the above-discussed data in the claims and the specification to clearly define distinct names for data associated with these circuits and units, the rejections of claims under 112 issues are certainly maintained.
Further, note that ¶ [0027] of the specification discloses: “The timing controller transmits image data to the display driving chip through a data bus …” and Fig. 3 shows “image data” outputted from the data alignment unit 240. A person skilled in the display or relevant art would have readily recognized that “image data transmitted from the timing controller” is not same/identical as/to “image data outputted from the data alignment unit 240” due to at least the operations and the processing delayed times of the circuits [221, 222] and units [230, 240] therebetween.
Further, note that the term “test pattern” must be also appropriately corrected when inputted/outputted into/from the circuit(s) and/or unit(s). See the above note regarding to the term “data”.
In summary, the whole disclosure, including the specification, claims and drawings, is not properly translated from the foreign applications and/or properly uses the appropriate terms/names to clearly define the distinct/different elements. Therefore, it is in the best interest of the patent community that applicant, in his/her normal review and/or rewriting of the disclosure, especially claims and, to take into consideration these editorial situations and make changes as necessary, in order to avoid at least unnecessary 112 issue(s).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per claim 1, this claim recites limitations, “a data alignment unit [[240]] that aligns data [[1]] recovered by the clock data recovery unit [[230]] and outputs the data [[2]] as image data; a bit error rate test unit that tests a bit error rate for the data [[1]] recovered by the clock data recovery unit [[230]] and outputs a result of the test” in lines 6-9. Note that the numbers in double square brackets are merely used for easily identifying elements in light of Fig. 3. As best understood in light of Fig. 3, “data [[1]]” is data outputted from the clock data recovery unit (CDR) 230 inputted to the data alignment unit [240] and “the data [[2]]”, as image data, is [[aligned]] data after “data [[1]]” is aligned/processed by the data alignment unit 240. Therefore, the data [[2]] is not same/identical as data [[1]] due to the operation and the processing delayed time by the data alignment unit [240]. Accordingly, there is insufficient antecedent basis for the limitation “the data [[2]]” in the claim.
As per claims 2-7, these claims are therefore rejected for at least the reason set forth in claim 1 above.
In addition to claim 3, this claim further recites a limitation, “wherein the equalization condition is the number of steps of equalization” in lines 1-2. Since “condition” and “number” are not same category, it is not clear what the above underlined limitation is meant, thereby rendering the above underlined limitation not clearly defined.
In addition to claim 4, this claim further recites a limitation, “wherein the equalization condition is a gain of an amplifier included in an equalizer circuit included in the data receiving unit” in lines 1-2. Since “condition” and “a gain of an amplifier” are not same category, it is not clear what the above underlined limitation is meant, thereby rendering the above underlined limitation not clearly defined.
In addition to claim 5, this claim further recites limitations, “wherein, in the equalization option controller, conditions of initial equalization input from a timing controller immediately after a power voltage of the display driving chip is applied or immediately after a power-on reset signal is applied are stored.” Since “conditions” are not signal(s), it is not clear how the “conditions” is input[[ted]] from a timing controller and what the above underlined limitations are meant, thereby rendering the above underlined limitations not clearly defined.
In addition to claims 6-7, these claims further recite a limitation, “the update” in line 1 of claim 6. There is insufficient antecedent basis for this limitation in the claims.
As per claim 8, this claim recites limitations, “a data receiving unit [[220]] that receives a test pattern [[1]] for testing a bit error rate; a clock data recovery unit [[230]] that recovers the test pattern [[2]] output from the data receiving unit according to a clock signal; a data alignment unit [[240]] that aligns the test pattern [[3]] recovered by the clock data recovery unit [[230]] and outputs the test pattern [[4]] as image data; and a bit error rate test unit that extracts a bit error rate of the test pattern [[3]] recovered by the clock data recovery unit” in lines 3-9. Note that the numbers in double square brackets are merely used for easily identifying elements in light of Fig. 3. As best understood in light of Fig. 3, test pattern [[1]] is a test pattern inputted/received at the data receiving unit [220], the test pattern [[2]] is a test pattern outputted from the data receiving unit [220], the test pattern [[3]] is a test pattern recovered and outputted by the clock data recovery unit [230], and the test pattern [[4]] is a test pattern outputted from the data alignment unit [240]. Therefore, test pattern [[1]], the test pattern [[2]], the test pattern [[3]], and the test pattern [[4]] all are different from each other, due to the operations and the processing delayed times by the units [220-240]. Accordingly, there is insufficient antecedent basis for the limitations “the test pattern [[2]]”, “the test pattern [[3]]”, and “the test pattern [[4]]” in the claim.
As per claims 9-10, these claims are therefore rejected for at least the reason set forth in claim 8 above.
In addition to claims 9-10, these claims further recite limitations, “the update” in line 1 of claim 9 and “the secondarily extracted result” in line 3 of claim 9. There is insufficient antecedent basis for these limitations in the claims.
In addition to claim 10, this claim further recites a limitation, “the updated storage” in last line. There is insufficient antecedent basis for this limitation in the claim.
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Note that, in order to satisfy its burden under the written description requirement, a patent application must disclose the full scope of the claim. Univ. of Rochester v. G.D. Searle & Co., 358 F.3d 916, 920 (Fed. Cir. 2004) (The purpose of the written description requirement is to “ensure that the scope of the right to exclude, as set forth in the claims, does not overreach the scope of the inventor’s contribution to the field of art as described in the patent specification.”.)
As per claim 1, this claim recites a limitation, “a data alignment unit that aligns data recovered by the clock data recovery unit and outputs the data as image data” in lines 6-7. The original disclosure, specifically Fig. 3 and paragraphs [0032]-[0033] of the specification, discloses that data, recovered by the clock data recovery unit [230], is realigned by the data alignment unit 240, in synchronized with the clock signal, to generate and output the aligned/deserialized data, as the resulted image data transmitted to the display panel. In other words, data recovered by the clock data recovery unit [230] is different from the aligned/deserialized data output[ted] from the data alignment unit 240. Further, see the above bolded note.
Moreover, a person skilled in the display or relevant art would have readily recognized that, data recovered by the clock data recovery unit [230] is different from the aligned/deserialized data output[ted] from the data alignment unit 240, due to at least the operations and the processing delayed times of the units [230, 240]. Otherwise, data recovered by the clock data recovery unit [230] can be directly outputted to the display panel without a need of the data alignment unit 240.
Accordingly, the original disclosure does not explicitly disclose in detail data recovered by the clock data recovery unit [230] being same as the [[aligned/deserialized]] data output[ted] from the data alignment unit 240, as required by the above underlined limitation of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 2-7, these claims are therefore rejected for at least the reason set forth in claim 1 above.
In addition to claims 6-7, these claims further recite a limitation, “wherein equalization by the update is inter-frame equalization executed in a section between data for each frame” in claim 6. This limitation is construed as “wherein equalization by the update is inter-frame equalization executed in a section between data in a frame.” The original disclosure, specifically Fig. 4, discloses inter-frame equalization [FEQ step] executed in a section between data for two adjacent frames, but does not explicitly discuss in detail inter-frame equalization [FEQ step] executed in a section between data a frame or each frame, of the above underlined limitation, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
As per claim 8, this claim recites a limitation, “a data alignment unit that aligns the test pattern recovered by the clock data recovery unit and outputs the test pattern as image data” in lines 6-7. The original disclosure, specifically Fig. 3, discloses that the test pattern, recovered by the clock data recovery unit [230], is realigned by the data alignment unit 240, in synchronized with the clock signal, to generate and output the aligned test pattern, as the resulted image data transmitted to the display panel. In other words, the test pattern recovered by the clock data recovery unit [230] is different from the aligned test pattern output[ted] from the data alignment unit 240. Further, see the above bolded note.
Moreover, a person skilled in the display or relevant art would have readily recognized that, the test pattern recovered by the clock data recovery unit [230] is different from the aligned test pattern output[ted] from the data alignment unit 240, due to at least the operations and the processing delayed times of the units [230, 240]. Otherwise, the test pattern recovered by the clock data recovery unit [230] can be directly outputted to the display panel without a need of the data alignment unit 240.
Accordingly, the original disclosure does not explicitly disclose in detail the test pattern recovered by the clock data recovery unit [230] being same as the [[aligned]] test pattern output[ted] from the data alignment unit 240, as required by the above underlined limitation of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 9-10, these claims are therefore rejected for at least the reason set forth in claim 8 above.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Due to the above rejections under 35 U.S.C. 112(a) and/or 35 U.S.C. 112(b), and for the sake of applying the prior art(s) in order to compact prosecution, the following art rejections are based as best understood by Examiner in view of the originally filed specification and drawings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 9,514,713 B2; hereinafter Lee) in view of Kamali (US 9,397,872 B2.)
As per claim 1, Lee discloses a display driving chip with a bit error rate test function (see at least Figs. 4A-4B, 6; Col. 8:7-46, disclosing a display driving chip comprising at least element [400/420; Figs. 4, 6] with a bit error rate test function,) comprising:
a data receiving unit that receives a test pattern (see at least Fig. 4A and the corresponding description at least Col. 7:55-64, disclosing the reception driver 421 receiving a packet including a data sequence from a timing controller;)
a clock data recovery unit that recovers an output signal of the data receiving unit according to a clock signal (see at least Fig. 4A and the corresponding description at least Col. 7:56 to Col. 8:6, disclosing a protocol decoder 422 and a CRC Decoder 424, for decoding a packet according to a predetermined protocol to extract display data and information included in the packet;)
a data alignment unit that aligns data recovered by the clock data recovery unit and outputs the data as image data (see at least Fig. 4A and the corresponding description at least Col. 7:56 to Col. 8:6, disclosing a protocol decoder 422 and a display data unit 423, for aligning data recovered by the clock data recovery unit and outputs the DSP data as image data to a screen;)
a bit error rate test unit that tests a bit error rate for the data recovered by the clock data recovery unit and outputs a result of the test (see at least Figs. 4A-4B and the corresponding description at least Col. 8:7-46, disclosing an error counter 425 for detecting bit errors with respect to display data and outputting a comparison result of a set level, wherein the timing controller selectively outputs a test pattern if a test mode is performed.)
Lee is silent to an equalization option controller for updating an equalization condition when a bit error rate exceeds a preset criterion, as claimed.
However, Kamali teaches a blind initialization technique, which is expected to operate within a predetermined time after power is turned on; and an optimal equalizer setting method that calculates bit error rate (BER) values for current equalizer settings and other equalizer settings and selects the setting that results in the lowest BER value (see at least Col. 1:40-53; claim 8,) thereby optimizing a high-speed link between a transmitter and a receiver (see at least Abstract; Col. 1:16-18.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to apply the aforementioned techniques, taught by the Kamali reference, in the display driving chip of Lee, to improve the above modified the display driving chip of Lee for the predictable result of optimizing a high-speed link between a transmitter (a timing controller of Lee) and a receiver (a source driver S/D of Lee.) Accordingly, the combination of Lee and Kamali obviously renders all limitations of this claim.
As per claim 2, Lee further discloses the test pattern being a pseudo random binary sequence (PRBS) pattern (see Lee at least Col. 19:15-22, disclosing: scrambling a test pattern.)
As per claim 5, the combination of Lee and Kamali obviously renders: wherein, in the equalization option controller, conditions of initial equalization input from a timing controller immediately after a power voltage of the display driving chip is applied or immediately after a power-on reset signal is applied are stored (see Kamali at least Col. 1:40-53, disclosing: using a blind initialization technique which is expected to operate within a predetermined time after power is turned on.)
As per claim 8, see the rejection of claim 1 for similar limitations. Note that “data” of claim 1 corresponds to “test pattern” of this claim. See Lee at least Col. 4:6-20; Col. 5:4-12, for data being test pattern. Also, see Kamali teaching a blind initialization technique, which is expected to operate within a predetermined time after power is turned on; and an optimal equalizer setting method that calculates bit error rate (BER) values for current equalizer settings and other equalizer settings and selects the setting that results in the lowest BER value, including an equalization option controller storing conditions of initial equalization (see at least Col. 1:40-53; claim 8.) Accordingly, the combination of Lee and Kamali obviously renders all limitations of this claim.
As per claim 9, the combination of Lee and Kamali obviously renders: wherein, after the update, the bit error rate is secondarily extracted, and a new equalization condition is separately stored in the equalizing operation controller based on the secondarily extracted result (see Kamali at least claim 6, disclosing: determining a first overall intersymbol interference (ISI) probability density function (PDF) from eye monitor data obtained for a current equalizer setting; extracting a channel ISI PDF from the first overall ISI PDF by using the current equalizer setting; generating a second overall ISI PDF for a different equalizer setting by using the channel ISI PDF; and determining an optimal equalizer setting on the basis of a comparison between the first overall ISI PDF and the second overall ISI PDF; note that a design change to steps readily derived.)
As per claim 10, the combination of Lee and Kamali obviously renders: wherein the equalization option controller stores the new equalization condition based on the secondarily extracted result separately from the updated storage (see Kamali at least claim 6, disclosing: determining a first overall intersymbol interference (ISI) probability density function (PDF) from eye monitor data obtained for a current equalizer setting; extracting a channel ISI PDF from the first overall ISI PDF by using the current equalizer setting; generating a second overall ISI PDF for a different equalizer setting by using the channel ISI PDF; and determining an optimal equalizer setting on the basis of a comparison between the first overall ISI PDF and the second overall ISI PDF; note that a design change to steps readily derived.)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kamali, as applied to claim 1 above, and further in view of Liao et al. (US 9,654,327 B2; hereinafter Liao.)
As per claim 4, the combination of Lee and Kamali is silent to “wherein the equalization condition is a gain of an amplifier included in an equalizer circuit included in the data receiving unit.” However, Liao discloses gain control and continuous time linear equalization performed on a signal through an automatic gain control (AGC) block and a continuous time linear equalization (CTLE) block, respectively, and feed-forward equalization is performed through a feed-forward equalization (FFE) block (see at least claim 13,) thereby dynamically changing signal channel transmission conditions to achieve at least a target error rate (see at least Col. 1:20-25.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to further modify the above modified display driving chip of Lee in view of Kamali to include the equalization condition being a gain of an amplifier included in an equalizer circuit included in the data receiving unit, in view of the teaching in the Liao reference, to improve the above modified the display driving chip of Lee for the predictable result of dynamically changing signal channel transmission conditions to achieve at least a target error rate. Accordingly, the combination of Lee, Kamali, and Liao obviously renders all limitations of this claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
Prosecution Insights