DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2022/0343877) in view of Lee et al. (US 2015/0130824).
As to claims 1 and 8, Park discloses a transmission and reception control method [0006, 0008]comprising: a step in which, in a first mode, a transmission device transmits an image signal to the reception device (external device of host through a display serial interface (Fig. 16, (DSI (800)) together with a synchronization signal [0020]; and a step in which, in a second mode, the transmission device transmits an image signal to the reception device without a synchronization signal, [0020], and when the command mode is set, writing image data received from the external device or host in a frame memory (Fig. 16, (50) through the DSI block (800) as an image to be displayed on a display panel (10) (Fig. 3, [0077, 0078]. However, Park does not specifically disclose at least one of a first interrupt signal and a second interrupt signal includes panel information to be applied to pixel data of an image signal.
Lee discloses a CPU (215) can analyze an interrupt signal (INT) and transmit, to timing controller (300) a signal (or a command or data) capable of removing an abnormality in a mobile industry processor interface (MIPI) interface (MIF) and/or an abnormality in the timing controller (300), on the basis of a result of the analysis, and the command can include a vertical active area (VAA) and a vertical blank area (BVA) (Figs. 2-3 and [0112, 0115, 0116, 0119], 0143]. It would have been obvious to one of ordinary skill in the art at the time of filing to have the interrupt signal, as taught by Lee, in the device of Park, since including panel information in the interrupt signal streamlines initialization, reduces host CPU load, improves timing accuracy, optimizes power, and simplifies driver design.
As to claim 2, Park, further, does not specifically disclose the panel information comprises one or more information of a compensation value to be applied to the pixel data of the image signal, location information of a defective subpixel, a refresh rate of a display panel, a bandwidth of the image signal, an interrupt signal period, and the number of pixel lines of the display panel.
Lee discloses the panel information comprises one or more information of a compensation value to be applied to the pixel data of the image signal, location information of a defective subpixel, a refresh rate of a display panel, a bandwidth of the image signal, an interrupt signal period, and the number of pixel lines of the display panel [0112, 0116, 0121, 0124](the command can include a VAA and a BVA). It would have been obvious to one of ordinary skill in the art at the time of filing to have the panel information, as taught by Lee, in the device of Park, since including panel information in the interrupt signal streamlines initialization, reduces host CPU load, improves timing accuracy, optimizes power, and simplifies driver design.
As to claim 3, Park discloses, further, in the first mode, the transmission device waits in a non-driving state during a vertical blank period until the first interrupt signal is detected [0089, 0095, 0186], and wakes up and transmits next frame data to the reception device when the first interrupt signal is detected [0089, 0095, 0186],, and a step in which, in the second mode, a synchronization signal is generated inside the reception device[0089, 0095, 0186].
As to claim 7, further, the first mode is a video mode of a mobile industry processor interface (MIPI)(DSI is the standard defined by the MIPI alliance), the second mode is a command mode of the MIPI(DSI is the standard defined by the MIPI alliance), the transmission device comprises one of a system on chip (SoC), an application processor (AP) [0097, 0177](a buffer unit can perform a CDC processing on an external synchronization signal inputted from a host in a video mode and an operation of delaying a signal inputted through the DSI (800)), and a graphics processing part (GPU), and the reception device comprises a display driver that outputs data of the image signal and outputs a display timing signal [0092, 0098, 00153].
Allowable Subject Matter
Claims 4-6 and 9-10 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 4-6 and 9-10 are indicated as allowable since certain key features of the claimed invention are not taught or fairly suggested by the prior art. In claim 4, “wherein at least one of the first interrupt signal and the second interrupt signal comprises at least one of a header part and a tail part, and at least one of the header part and the tail part comprises a pulse toggled at a cycle of n (n is a positive integer) horizontal period and having a pulse width of n horizontal period, or two or more impulses generated at a cycle of n horizontal period“. In claims 6, and 10 “wherein at least one of the first interrupt signal and the second interrupt signal comprises: a first header part toggled at a cycle of n (n is a positive integer) horizontal period; a second header part comprising information on an information section in which the panel information is encoded; a first tail part comprising an error check code; and a second tail part toggled at a cycle of n horizontal period, an interrupt signal period during which at least one of the first interrupt signal and the second interrupt signal is transmitted to the transmission device (host processor) comprises: a 1-ith period during which the first header part is transmitted to the transmission device; a 1-2th period during which the second header part is transmitted to the transmission device (host processor); a second period during which the information section in which the panel information is encoded is transmitted to the transmission device (host processor); a 3-ith period during which the first tail part is transmitted to the transmission device (host processor); and a 3-2th period during which the second tail part is transmitted to the transmission device(host processor)”. As to claim 9, “wherein the interrupt signal comprises one or more of a header part transmitted to the transmission device before an information section including the panel information and a tail part transmitted to the transmission device after the information section, one or more of the header part and the tail part comprise a signal toggled at a cycle of n (n is a positive integer) horizontal period, and an interrupt signal period during which the interrupt signal is transmitted to the host processor comprises: a first period during which the header part is transmitted to the host processor; a second period during which the information section is transmitted to the host processor; and a third period during which the tail part is transmitted to the host processor”. The closest prior art, (see Park (US 2022/0343877) above), however, singularly or in combination, fails to anticipate or render the above underlined limitations obvious, together with all the other limitations of the claims.
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/RICARDO OSORIO/Primary Examiner, Art Unit 2625
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