DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/2026 has been considered by the examiner, except where lined-through. US Patent Application Publication number is incorrect. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Patent Publication No. 2020/0211476; hereinafter Park) in view of Sugawara et al. (US Patent Publication No. 2023/0168768; hereinafter Sugawara).
With reference to claim 1, Park discloses an OLED display (see paragraph 27; Fig. 1) comprising:
a plurality of sub-pixels (P) (see paragraph 28; Figs. 1, 3);
wherein each of the plurality of sub-pixels (P) comprises:
a first conduction circuit (T5), a second conduction circuit (DT), and a pixel electrode (anode electrode of the OLED; see paragraph 40, 46, 56; Fig. 3);
in a same sub-pixel (P), the first conduction circuit (T5) and the second conduction circuit (DT) are both coupled to the pixel electrode (OLED) (see paragraphs 46, 56; Figs. 3);
the first conduction circuit (T5) is configured to provide a reset signal (initialization voltage) from a reset signal terminal (Vint) to the pixel electrode (OLED) in response to a signal from a first control signal terminal (SCAN(n-1); see paragraph 46; Fig. 6);
the second conduction circuit (T3) is configured to provide a data signal from a data signal terminal (Vdata; see paragraph 31) to the pixel electrode (OLED) in response to a signal (EM(n-1)) from a second control signal terminal (gate of T3) (the third transistor (T3) provides the high potential driving voltage VDD to the third node (N3) in response to the emission signal (EM(n-1)) (see paragraph 44; Figs. 6-7), and in the emission period (De) the third transistor (T3) and the fourth transistor (T4) are turned on, and a driving current from the input terminal of the high potential driving voltage (VDD) via the driving transistor (DT) enters an anode electrode of the OLED; see paragraph 56-57; Figs. 6-7); and
the first conduction circuit (T5) and the second conduction circuit (DT) in the same sub-pixel (see Fig. 3) work in a time-division manner (in teaching time periods in which turn-on voltages and turn-off voltages; see paragraphs 51-52, 55-56; Figs. 4, 6-7), and
a gate driving circuit (500) (see paragraph 27; Fig. 1), comprising a plurality of shift registers (510, 520) (see paragraphs 34; Figs. 1-3); wherein the first control signal terminal (SCAN(n-1); see paragraph 46; Fig. 6) corresponding to the first conduction circuit (T5) and the second control signal terminal (gate of T3) corresponding to the second conduction circuit (T3) in the same sub-pixel (HL2) are connected to different shift registers (510, 520) (see paragraphs 35-36; Figs. 2-3).
While teaching the sub-pixel arrangement as recited, Park fails to specifically disclose the usage of an electronic paper display panel as recited.
Sugawara discloses an electronic paper display panel having a plurality of sub-pixels (SPXn) (see paragraphs 27, 32; Figs. 4-5).
Therefore it would have been obvious to one of ordinary skill in the art to allow the usage of an electronic paper display panel having the sub-pixel arrangement similar to that which is taught by Park, as an alternative display panel type (see Sugawara; paragraph 32).
With reference to claim 2, Park and Sugawara disclose the electronic paper display panel according to claim 1, Park further discloses wherein the first conduction circuit comprises a first transistor (T5); a gate of the first transistor is coupled to the first control signal terminal (SCAN(n-1); see paragraph 46; Fig. 6), a first electrode of the first transistor is coupled to the reset signal terminal (Vinit; see paragraph 46), and a second electrode of the first transistor (T5) is coupled to the pixel electrode (anode electrode of the OLED; see paragraph 40, 46, 56; Fig. 3).
With reference to claim 3, Park and Sugawara disclose the electronic paper display panel according to claim 1, Park further discloses wherein the second conduction circuit comprises a second transistor (T3); a gate of the second transistor (T3) is coupled to the second control signal terminal (EM(n-1)), a first electrode of the second transistor (T3) is coupled to the data signal terminal (Vdata) (via N3; see paragraphs 43-44; Figs. 6-7), and a second electrode of the second transistor (T3) is coupled to the pixel electrode (OLED) (via DT; see paragraphs 53, 56; Figs. 3, 6-7).
With reference to claim 4, Park and Sugawara disclose the electronic paper display panel according to claim 1, Park further discloses a plurality of first scan signal lines (plurality of gate lines GL1 to GL(n); see paragraph 28; Fig. 1) and a plurality of second scan signal lines (emission line; see paragraph 29; Fig. 1); wherein, first control signal terminals (SCAN(n-1)) corresponding to a row of sub-pixels (P) are all coupled to one of the plurality of first scan signal lines (GL1-to GL(n) can include a scan line; see paragraph 29; Fig. 3); and second control signal terminals (gate of T3) corresponding to the row of sub-pixels (P) are all coupled to one of the plurality of second scan signal lines (GL1-to GL(n)) can include an emission line; see paragraph 29; Fig. 3).
With reference to claim 5, Park and Sugawara disclose the electronic paper display panel according to claim 4, Park further discloses wherein, the plurality of shift registers (510, 520) comprises: a plurality of first shift registers (SDn) and a plurality of second shift registers (EMDn); one of the plurality of first shift registers (SDn) is coupled to one of the plurality of first scan signal lines (SCANn); one of the plurality of second shift registers (EMDn) is coupled to one of the plurality of second scan signal lines (EMn) (see paragraphs 68-70; Fig. 2).
With reference to claim 6, Park and Sugawara disclose the electronic paper display panel according to claim 4, Park further discloses wherein, the plurality of shift registers (510, 520) comprises: a plurality of third shift registers; one of the plurality of third shift registers is coupled to one of the plurality of first scan signal lines (SCANn); the first scan signal line (SCANn) corresponding to the m-th row of sub-pixels (HL2) is coupled to the second scan signal line (EMn) corresponding to the n-th row of sub-pixels (HL1), wherein m is greater than n; and both m and n are positive integers (see paragraphs 68-70; Fig. 2).
With reference to claim 7, Park and Sugawara disclose the electronic paper display panel according to claim 1, Sugawara further discloses a plurality of reset signal lines (GLrst(n)) and a plurality of data lines (SL(n)) (see paragraphs 54, 67; Fig. 5); reset signal terminals (Mrst) corresponding to a column of sub-pixels (SPXn) are coupled to one of the plurality of reset signal lines (GLrst) (see paragraphs 57; Fig. 5); data signal terminals (Tr) corresponding to the column of sub-pixels (SPXn) are coupled to one of the plurality of data lines (SL) (see paragraph 54; Fig. 5).
With reference to claim 10, Park and Sugawara disclose an electronic paper display panel according to claim 7, Park further discloses wherein the plurality of reset signal lines (Scan (n-1)) are coupled with each other (in teaching gate lines GL1 (SCAN(n-1) wherein each pixel are connected to the same gate line; see paragraphs 28-29; Figs. 1-3).
With reference to claim 11, Park and Sugawara disclose the electronic paper display panel according to claim 1, Park further discloses a plurality of data lines (DLn) and a plurality of source driving input terminals (the second transistor (T2) writes the data voltage (Vdata) from the data line (DL); see paragraph 52; Figs. 1, 3); wherein a column of sub-pixels (P) corresponds to one of the plurality of data lines (DLn) and one of the plurality of source driving input terminals (T2) (see paragraphs 31, 43; Fig. 1); data signal terminals (300) corresponding to the column of sub-pixels are coupled to the source driving input terminal (T2) through the data line (DL) (see paragraphs 31, 43, 52; Figs. 1, 3).
With reference to claim 12, Park and Sugawara disclose the electronic paper display panel according to claim 1, Sugawara further discloses a first base substrate (21) (see paragraph 26; Fig. 1); wherein the plurality of sub-pixels (PXn) are located at a side of the first base substrate (21) (see paragraph 26; Figs. 1-2); each of the plurality of sub-pixels (PXn) further comprises: a common electrode (counter substrate; 22), located at a side of the pixel electrode (21) facing away from the first base substrate (2) (see paragraphs 26-27; Fig. 2); and an electrophoretic liquid layer, located between the pixel electrode and the common electrode, and the electrophoretic liquid layer comprising a plurality of charged particles (in teaching the usage of an electrophoretic display panel using electrophoretic elements as display elements; see paragraph 32); wherein the pixel electrode is configured to drive the plurality of charged particles (corresponding to the sub-pixels (SPX)) to a adjust grayscale display (see paragraphs 27-28).
With reference to claim 13, Park and Sugawara disclose a display apparatus, comprising the electronic paper display panel according to any one of claims claim 1 (see Sugawara; paragraph 32).
With reference to claim 14, Park and Sugawara disclose a method for driving the electronic paper display panel according to claim1, wherein Park further discloses in a first stage (D1), in response to the signal from the first control signal terminal (SCAN(n-1); see paragraph 46; Figs. 4, 6), providing, by the first conduction circuit (T5), the reset signal from the reset signal (initialization voltage) terminal (Vint) to the pixel electrode (OLED) (see paragraphs 46, 49; Figs. 4, 6); in a second stage (Ds, De), in response to the signal from the second control signal terminal (gate of T3), providing, by the second conduction circuit (T3), the data signal from the data signal terminal (Vdata) to the pixel electrode (OLED) (see paragraphs 51, 55-56; Figs. 4, 6-7); wherein the first conduction circuit (T5) and the second conduction circuit (T3) in the same sub-pixel work in the time-division manner (see paragraphs 48; Fig. 4).
With reference to claim 15, Park and Sugawara disclose a driving method of the electronic paper display panel according to claim 14, wherein Park further discloses wherein potentials of the reset signal (SCAN(n-1)) and the data signal (EM(n-1)) provided to the pixel electrode (OLED) in the same sub-pixel are opposite to each other (see Fig. 4).
With reference to claim 16, Park and Sugawara disclose a driving method of the electronic paper display panel according to claim 14, wherein Park further discloses wherein the potential of the reset signal provided to the pixel electrode in each of the sub-pixels is a fixed potential (in teaching constant on/off voltage potentials (SCAN(n-1); see Fig. 4).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Sugawara as applied to claim 1 above, and further in view of Kim et al. (US Patent Publication No. 2021/0201798; hereinafter Kim).
With reference to claim 8, Park and Sugawara disclose the electronic paper display panel according to claim 8, however fail to disclose a plurality of gating control circuits as recited.
Kim discloses an OLED display panel (see Fig. 1) comprising: a plurality of gating control circuits (circuitry connected to each Vdata line of multiplexer (50) consisting of SW1 and SW2; see Fig. 2) and a plurality of source driving input terminals (Vdata) (see paragraph 46; Fig. 2); wherein, the column of sub-pixels (OLED array of display panel (10); see paragraph 36; Fig. 1) corresponds to one gating control circuit of the plurality of gating control circuits (SW1, SW2; see Fig. 2) and one source driving input terminal (Vdata) of the plurality of source driving input terminals (see Fig. 2); the source driving input terminal (Vdata) is coupled to the reset signal line (SEL A) and the data line (DL) of the corresponding column of sub-pixels through the gating control circuit (SW1, SW2) (see paragraphs 41, 50; Figs. 1-2), and the gating control circuit (SW1, SW2) is configured to provide a signal from the source driving input terminal (30, Vdata) to the reset signal line (SEL B) in response to a signal from a first gating control terminal (SW2), and to provide the signal from the source driving input terminal (30, Vdata) to the data line (DL) in response to a signal from a second gating control terminal (SW1) (see paragraphs 51-52; Figs. 1-2).
Therefore it would have been obvious to one of ordinary skill in the art to allow the usage of a gating control circuit similar to that which is taught by Kim to be carried out in a display similar to that which is taught by Park and Sugawara to provide an OLED device which is capable of improving power consumption (see Kim; paragraph 8).
With reference to claim 9, Park and Sugawara disclose the electronic paper display panel according to claim 8, wherein, Kim further discloses the gating control circuit (SW1, SW2) comprises: a first gating control transistor (SW2) and a second gating control transistor (SW1) (see paragraph 50; Fig. 2); a gate of the first gating control transistor (SW2) is coupled to the first gating control terminal (SEL A), a first electrode of the first gating control transistor is coupled to the reset signal line (Vpark), and a second electrode of the first gating control transistor (SW2) is coupled to the source driving input terminal (Vdata via SW1); a gate of the second gating control transistor (SW1) is coupled to the second gating control terminal (SEL A), a first electrode of the second gating control transistor is coupled to the data line (DL), and a second electrode of the second gating control transistor is coupled to the source driving input terminal (Vdata) (see paragraphs 51-52; Fig. 2).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JOHNSON et al. (US2006/0152473) discloses an electrophoretic display device counter electrodes facing away from the pixel electrodes with electrophoretic medium provided therebetween (see paragraphs 38-49; Figs. 1-3).
ZHOU et al. (US2005/0162377) discloses a display device comprising a display element comprising a pixel electrode and an associated counter electrode, between which a portion of electrophoretic particles is present and a controller for supplying drive signals to the electrode (see abstract, paragraphs 42-43, 50-57; Figs. 1-11).
Conclusion
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/Alecia D English/ Examiner, Art Unit 2625
571-270-1595
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