DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 8-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0168195 to Kumeta et al.
As per claim 1, Kumeta et al. teach a pixel circuit, comprising:
a driving transistor (Fig. 12, 101), a light-emitting device (Fig. 12, 106), a compensation sub-circuit (Fig. 12, 102), and a coupling sub-circuit (Fig. 12, 105);
wherein a first electrode of the driving transistor is coupled with a first power supply end and is configured to generate a driving current according to a data voltage, wherein the first power supply end is written with the data voltage (Fig. 12, DT) and a first power supply voltage (Fig. 12, ELVDD) in a time-sharing manner (Figs. 12 and 13, signals DAON and VTON are complementary);
the compensation sub-circuit (Fig. 12, 102) is coupled with a gate of the driving transistor and a second electrode of the driving transistor and is configured to connect the gate of the driving transistor and the second electrode of the driving transistor in response to a signal of a scan signal end (Fig 12, SCAN);
the coupling sub-circuit (Fig. 12, 105) is coupled with the gate of the driving transistor and is configured to change a voltage of the gate of the driving transistor in response to a signal of a gating control end (Figs. 12 and 13, see signal VCST);
an anode of the light-emitting device (Fig. 12, 106) is coupled with the second electrode of the driving transistor, a cathode of the light-emitting device is coupled with a second power supply end (Fig. 12, ELVSS), and the light-emitting device is configured to emit light under an action of the driving current.
As per claim 2, Kumeta et al. teach the pixel circuit according to claim 1, wherein the compensation sub-circuit comprises: a first transistor (Fig. 12, 102); a control end of the first transistor is coupled with the scan signal end, a first end of the first transistor is coupled with the gate of the driving transistor, and a second end of the first transistor is coupled with the anode of the light-emitting device (Fig. 12, coupled to the anode, at least indirectly via 103).
As per claim 3, Kumeta et al. teach the pixel circuit according to claim 1, wherein the coupling sub-circuit comprises: a first capacitor (Fig. 12, 105); a first end of the first capacitor is coupled with the gating control end (Figs. 12 and 13, see signal VCST), and a second end of the first capacitor is coupled with the gate of the driving transistor.
As per claim 6, Kumeta et al. teach the pixel circuit according to claim 2, wherein the first transistor is a single-gate transistor (Fig. 12, 102) or a dual-gate transistor; based on that the first transistor is the dual-gate transistor, a first gate of the first transistor is coupled with the scan signal end, and a second gate of the first transistor is coupled with the scan signal end.
As per claim 8, Kumeta et al. teach a display panel, comprising: a plurality of pixels (Fig. 5, 100), wherein each of the plurality of pixels comprises the pixel circuit according to claim 1.
As per claim 9, Kumeta et al. teach the display panel according to claim 8, comprising a gating signal line; wherein the gating control end of each of the plurality of pixels is coupled with the same gating signal line (Fig. 5, all pixels in a same row share a same scan line).
As per claim 10, Kumeta et al. teach the display panel according to claim 8, comprising: a plurality of reset lines and a plurality of gate lines; wherein reset signal ends of pixel circuits in a row of pixels are coupled with one of the plurality of reset lines, and gate control ends in a row of pixels are coupled with one of the plurality of gate lines (Figs. 5 and 12).
As per claim 11, Kumeta et al. teach the display panel according to claim 10, wherein a reset control circuit is coupled with the reset lines (Figs. 5, 6 and 12, means for generating reset signals), a gate driving circuit is coupled with the gate lines (Fig. 5, 6 and 12, means for generating gate signals), and a source driving circuit is coupled with a gating signal line (Fig. 5, 6 and 12, means for generating gating signals).
As per claim 12, Kumeta et al. teach a display apparatus, comprising the display panel according to claim 8 (paragraph 97, “an electro-optic device formed according to the second embodiment may include a number of additional peripheral circuits, such as a gate signal line driving circuit, a data signal line driving circuit, a controller controlling data signals, etc”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 7, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0168195 to Kumeta et al.; in view of US 2022/0199010 to Zhao et al..
As per claim 4, Kumeta et al. teach the pixel circuit according to claim 1, further comprising a reset sub-circuit (Fig. 12, 104); wherein the reset sub-circuit is configured to provide an initialization signal at an initialization signal end to the gate of the driving transistor in response to a signal of a reset signal end (paragraph 70, “the initial voltage is applied to the gate of driving transistor 101”, paragraph 77, “Also, during the reset period, third transistor 104 may be turned on. At this time, a gate voltage of a driving transistor 101 may be reset to an initial voltage”).
Kumeta et al. do not teach wherein the reset sub-circuit is coupled with the anode of the light-emitting device and the initialization signa is provided to the anode of the light-emitting device.
Zhao et al. teach wherein the reset sub-circuit (Fig. 5, ST5) is coupled with the anode of the light-emitting device and the initialization signal is provided to the anode of the light-emitting device (Figs. 5 and 6, paragraph 107, “In the second stage T11, … the second light emission control signal EM2, the first scanning signal Scan1 and the second scanning signal Scan2 are at a low level. The … second transistor ST2, the fourth transistor ST4 and the fifth transistor ST5 are on, and the reference voltage signal Vref is written into the gate electrode of the drive transistor DTFT through the fourth transistor ST4 and the fifth transistor ST5 … The reference voltage signal Vref is written into the anode of the light emission device OLED through the fifth transistor ST5 and the second transistor ST2”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Kumeta et al., so that the reset sub-circuit is coupled with the anode of the light-emitting device and the initialization signa is provided to the anode of the light-emitting device, such as taught by Zhao et al., because it performs the same function of initializing voltages before a data writing operation.
As per claim 5, Kumeta and Zhao et al. teach the pixel circuit according to claim 4, wherein the reset sub-circuit comprises: a second transistor (Fig. 5, ST5); a control end of the second transistor is coupled with the reset signal end (Fig. 5, Scan2), a first end of the second transistor is coupled with the anode of the light-emitting device (paragraph 107, “The reference voltage signal Vref is written into the anode of the light emission device OLED through the fifth transistor ST5 and the second transistor ST2”), and a second end of the second transistor is coupled with the initialization signal end (Fig. 5, Vref).
As per claim 7, Kumeta and Zhao et al. teach the pixel circuit according to claim 4, wherein the initialization signal end and the gating control end are the same signal end (Zhao, Fig. 4, both Scan1 and Scan2 ends have the same signal).
As per claim 13, Kumeta et al. teach a driving method for the pixel circuit according to claim 1, comprising: in a reset stage (Fig. 3, (a)): a reset sub-circuit (Fig. 12, 104 controlled by signal INIT) providing an initialization signal to the gate of the driving transistor in response to a signal of a reset signal end;
in a data writing stage (Fig. 3, (c)): the compensation sub-circuit (Fig. 12, 102 controlled by signal SCAN) connecting the gate of the driving transistor and the second electrode of the driving transistor in response to the signal of the scan signal end;
in a light-emitting stage (Fig. 3 (d)): the coupling sub-circuit (Fig. 12, 105 receiving VCST) changes the voltage of the gate of the driving transistor in response to the signal of the gating control end, so that the driving transistor generates the driving current according to the data voltage and the light-emitting device emits light under the action of the driving current.
Kumeta et al. do not teach providing the initialization signal to the anode of the light-emitting device.
Zhao et al. teach providing the initialization signal to the anode of the light-emitting device (Figs. 5 and 6, paragraph 107, “In the second stage T11, … the second light emission control signal EM2, the first scanning signal Scan1 and the second scanning signal Scan2 are at a low level. The … second transistor ST2, the fourth transistor ST4 and the fifth transistor ST5 are on, and the reference voltage signal Vref is written into the gate electrode of the drive transistor DTFT through the fourth transistor ST4 and the fifth transistor ST5 … The reference voltage signal Vref is written into the anode of the light emission device OLED through the fifth transistor ST5 and the second transistor ST2”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Kumeta et al., by providing the initialization signal to the anode of the light-emitting device, such as taught by Zhao et al., because it performs the same function of initializing voltages before a data writing operation.
As per claim 14, Kumeta and Zhao et al. teach the driving method for the pixel circuit according to claim 13, wherein: each display frame comprises a first stage and a second stage, the driving method comprises: driving the pixel circuit in each pixel row by row to perform the reset stage and the data writing stage in the first stage (Fig. 6, scan signals are sequentially applied, as per Fig. 3, reset signals precede scan signals); controlling the pixel circuit in each pixel to perform the light-emitting stage in the second stage (Fig. 3(d), paragraph 100, “When the data update period ends, a light-emitting control signal EM may be provided such that all pixels operation in a light-emitting state to thereby emit light according to gate voltages of their respective driving transistors”).
Conclusion
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622
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