DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “wherein the display area comprises a plurality of sub-pixels and a plurality of control signal lines; wherein each of the plurality of sub-pixels comprises a pixel circuit, and the pixel circuit comprises: a light-emitting device, a driving transistor, a data writing circuit, and a pixel control circuit; wherein the driving transistor is coupled to the data writing circuit and the pixel control circuit respectively, the data writing circuit is configured to provide a data voltage at a data signal terminal to a gate of the driving transistor in response to a scan signal at a scan signal terminal, and the pixel control circuit is configured to control the driving transistor to generate a driving current for driving the light-emitting device to emit light;”.
The claim sentence is long and there are multiple “;” in this sentence.
Examiner suggests applicant to break this limitation to improve claim clarity for claim interpretation.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Long et al. (US 20210407424 A1, Published date 12/30/2021) in view of Zhou et al. (U.S. Patent Publication 20230098040 A1).
Regarding claim 1, Long discloses A display panel comprising a display area and a non-display area; ([0003] – [0005])
wherein the display area comprises a plurality of sub-pixels and a plurality of control signal lines; ([0003] – [0005]) wherein each of the plurality of sub-pixels comprises a pixel circuit, (Fig. 2, [0063] pixel circuit 100) and the pixel circuit comprises: a light-emitting device (Fig. 2, D1), a driving transistor (Fig. 2, [0064] The driving sub-circuit 110 is configured to control a driving current for driving the light-emitting element D1 to emit light. For example, the driving sub-circuit 110 may be implemented as a first transistor T1, a gate electrode of the first transistor T1 is connected to a first node N1, a first electrode of the first transistor T1 is connected to a second point N2, and a second electrode of the first transistor T1 is connected to a third node N3.), and a pixel control circuit (Fig. 2, [0067] The light-emission control sub-circuit 140 is configured to apply the first voltage VDD to the driving sub-circuit 110 in response to a light-emission control pulse signal EM3 and cause the driving current of the driving sub-circuit 110 to be applied to the light-emitting element D1. For example, the driving current is applied to the anode of the light-emitting element D1.)), a data writing circuit; (Fig. 2, [0066] The compensation sub-circuit 130 is configured to store the data signal DATA that is written therein, and compensate the driving sub-circuit 110 in response to the scan signal GATE. For example, the compensation sub-circuit 130 may be implemented to include a third transistor T3 and a storage capacitor CST. A gate electrode of the third transistor T3 is configured to receive the scan signal GATE, a first electrode of the third transistor T3 is connected to the third node N3, a second electrode of the third transistor T3 is connected to a first electrode of the storage capacitor CST (that is, the first node N1), and a second electrode of the storage capacitor CST is configured to receive a first voltage VDD.) wherein the driving transistor is coupled to the data writing circuit and the pixel control circuit respectively, (Fig. 2, 110 couple to 130 and 140) the data writing circuit is configured to provide a data voltage at a data signal terminal to a gate of the driving transistor in response to a scan signal at a scan signal terminal, (Fig. 2, [0066] The compensation sub-circuit 130 is configured to store the data signal DATA that is written therein, and compensate the driving sub-circuit 110 in response to the scan signal GATE. For example, the compensation sub-circuit 130 may be implemented to include a third transistor T3 and a storage capacitor CST. A gate electrode of the third transistor T3 is configured to receive the scan signal GATE, a first electrode of the third transistor T3 is connected to the third node N3, a second electrode of the third transistor T3 is connected to a first electrode of the storage capacitor CST (that is, the first node N1), and a second electrode of the storage capacitor CST is configured to receive a first voltage VDD.) and the pixel control circuit is configured to control the driving transistor to generate a driving current for driving the light-emitting device to emit light; ([0067] The light-emission control sub-circuit 140 is configured to apply the first voltage VDD to the driving sub-circuit 110 in response to a light-emission control pulse signal EM3 and cause the driving current of the driving sub-circuit 110 to be applied to the light-emitting element D1. For example, the driving current is applied to the anode of the light-emitting element D1. For example, the light-emission control sub-circuit 140 may be implemented to include a fifth transistor T5 and a sixth transistor T6. A gate electrode of the fifth transistor T5 is configured to receive the light-emission control pulse signal EM3, a first electrode of the fifth transistor T5 is configured to receive the first voltage VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is configured to receive the light-emission control pulse signal EM3, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the light-emitting element D1.)
pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one control signal line among the plurality of control signal lines, (Fig .1 pixel 100 in one row connected to EML [0060] [0137] – [0140]) and control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other; (Fig. 1, SCDC connected to two adjacent rows of 100 [0149] – [0152])
Long does not disclose “the non-display area comprises a drive control circuit, and the drive control circuit comprises a plurality of shift register units; wherein the control signal lines coupled to each other are coupled to one shift register unit among the plurality of shift register units, and the shift register unit is configured to transmit a signal to pixel circuits through the control signal lines.”
Zhou discloses “the non-display area comprises a drive control circuit, and the drive control circuit comprises a plurality of shift register units; (Fig. 11, [0050] As shown in FIG. 1, the display panel includes at least two driving circuits 20 located in the non-display area NA. The driving circuit 20 can include shift registers 30 that are cascaded. The shift register 30 is any structure configured to shift signals.) wherein the control signal lines coupled to each other are coupled to one shift register unit among the plurality of shift register units, and the shift register unit is configured to transmit a signal to pixel circuits through the control signal lines.” (Fig. 11, [0050] [0056] [0062] [0063] [0073])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate shift register by Zhou into device of Long. The suggestion/motivation would have been to provide shift signals. (Zhou: [0050])
Regarding claim 2, Long and Zhou disclose wherein the pixel circuit comprises a first light emitting control circuit; (Long Fig. 11 140) wherein the first light emitting control circuit is coupled to a first electrode of the driving transistor (Long Fig. 11 110) , a first light emitting control signal terminal and a first power terminal; (Long Fig. 11 VDD) and the first light emitting control circuit is configured to provide a signal at the first power terminal to the first electrode of the driving transistor in response to a first light emitting control signal at the first light emitting control signal terminal; the display area further comprises a plurality of first light emitting control signal lines; (Long Fig. 11 [0120] – [0129] wherein first light emitting control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one first light emitting control signal line among the plurality of first light emitting control signal lines. (Long Fig. 11 [0120] – [0129]
Regarding claim 7, Long and Zhou disclose wherein the pixel circuit comprises a second light emitting control circuit; (Long Fig. 11 140) the second light emitting control circuit is coupled to a second electrode of the driving transistor, (Long Fig. 11 110), the light- emitting device and a second light emitting control signal terminal; (Long Fig. 11 [0120] – [0129] the second light emitting control circuit is configured to enable conduction between the second electrode of the driving transistor and the light-emitting device in response to a second light emitting control signal at the second light emitting control signal terminal; (Long Fig. 11 [0120] – [0129]
the display area further comprises a plurality of second light emitting control signal lines; wherein second light emitting control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one second light emitting control signal line among the plurality of second light emitting control signal lines. (Long Fig. 11 [0120] – [0129]
Claims 12, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Long et al. (US 20210407424 A1, Published date 12/30/2021) in view of Zhou et al. (U.S. Patent Publication 20230098040 A1) in view of Yuan et al. (U.S. Patent Publication 20230080385 A1).
Regarding claim 12, Long and Zhou do not disclose wherein the pixel circuit comprises a first reset control circuit; the first reset control circuit is coupled to the gate of the driving transistor, a first reset control signal terminal and a reference signal terminal; the first reset control circuit is configured to provide a signal at the reference signal terminal to the gate of the driving transistor in response to a first reset control signal at the first reset control signal terminal; the display area further comprises a plurality of first reset control signal lines; wherein first reset control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one first reset control signal line among the plurality of first reset control signal lines.
Yuan discloses wherein the pixel circuit comprises a first reset control circuit; ([0011]) the first reset control circuit is coupled to the gate of the driving transistor, a first reset control signal terminal and a reference signal terminal; ([0154] [0135] [0133] )
the first reset control circuit is configured to provide a signal at the reference signal terminal to the gate of the driving transistor in response to a first reset control signal at the first reset control signal terminal; ([0154] [0135] [0133] ) the display area further comprises a plurality of first reset control signal lines; ([0154] [0135] [0133] )
wherein first reset control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one first reset control signal line among the plurality of first reset control signal lines. ([0154] [0135] [0133] )
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate reset circuit by Yuan into device of Long and Zhou. The suggestion/motivation would have been to provide reset signals. (Yuan: [0011])
Regarding claim 17, Long and Zhou do not disclose wherein the pixel circuit comprises a second reset control circuit; the second reset control circuit is coupled to a second electrode of the driving transistor, a second reset control signal terminal and a first initialization signal terminal; the second reset control circuit is configured to provide a signal at the first initialization signal terminal to the second electrode of the driving transistor in response to a second reset control signal at the second reset control signal terminal; the display area further comprises a plurality of second reset control signal lines; wherein second reset control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one second reset control signal line among the plurality of second reset control signal lines.
Yuan discloses wherein the pixel circuit comprises a second reset control circuit; [[0011] the second reset control circuit is coupled to a second electrode of the driving transistor, a second reset control signal terminal and a first initialization signal terminal; ([0154] [0135] [0133] )
the second reset control circuit is configured to provide a signal at the first initialization signal terminal to the second electrode of the driving transistor in response to a second reset control signal at the second reset control signal terminal; ([0154] [0135] [0133] )
the display area further comprises a plurality of second reset control signal lines; ([0154] [0135] [0133] ) wherein second reset control signal terminals of pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one second reset control signal line among the plurality of second reset control signal lines. ([0154] [0135] [0133])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate reset circuit by Yuan into device of Long and Zhou. The suggestion/motivation would have been to provide reset signals. (Yuan: [0011])
Allowable Subject Matter
Claims 3 – 6, 8 – 11, 13 – 16, 18 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160293103 A1 discloses LED driving circuit on Fig. 2
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN-NAN LIN whose telephone number is (571)272-5646. The examiner can normally be reached Monday - Thursday 7:30am - 6pm.
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/CHUN-NAN LIN/Primary Examiner, Art Unit 2629
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