Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 25, 2025, is in compliance with the provisions of 37 CFR 1.97. And accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Peng et al (PG Pub NO 2019/0318706).
As in claim 1, Peng et al discloses a display system (Par 0002 and Fig 4) comprising:
a display for presentation to a user; (Par 0072 and FIG. 4) discloses a display system 25 include an electronic display 50
a pixel panel including a first pixel and a second pixel, the first pixel having a first performance capability with respect to a criterion and the second pixel having a second performance capability with respect to the criterion; (Fig 2, 3 and Par 0067, 0071 & 0072) discloses [0067] FIG. 2A schematically illustrates a portion of a light emitting surface of display 10 with a 2D array of pixels 20; although only a 4×4 segment of the array is shown, a typical 2D display may include hundreds or thousands of pixels in at least one dimension. Each pixel 20 may include one or more active areas 21 which in operation emit or transmit image light, and which may include one or more subpixels. [0072] The pixelated display 50 includes an array of pixels, each pixel including one or more active areas that are configured to emit or transmit light in response to receiving image data, and interstitial spaces that may appear as dark to a viewer when ISD 60 is absent. The number of pixels in the pixel array of display 50 defines a native resolution of the display. By way of example, the pixel array of the display 50 may be a rectangular array of size N×M, with N pixel columns and M pixel rows. [0071] A second pixel adjacent to a first pixel can be defective and has a second performance capability with respect to the first pixel in that it no longer operates or operates at a lower light level than desired.
and a pixel controller configured to cause the display system to present a frame on the display by performing operations including: causing first light emitted by the first pixel to be displayed at a pixel position on the display during presentation of a first subframe of the frame; and causing second light emitted by the second pixel to be displayed at the pixel position on the display during presentation of a second subframe of the frame. (Par 0071) discloses Image pixels 41-44 prior to the shift may be said to belong to a first subframe image, and image pixels 41a-44a after the shift may be said to belong to a second subframe image. [0079] In some embodiments the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. In such embodiments the subframes 73 may be of the same resolution as the input image frame 71, but may represent the corresponding scene or pattern sampled with a sampling offset varying by a pixel pitch of the display 50, or an integer number thereof. In some embodiments two consecutive subframes 73 may each be substantially a same input frame 71 with a counter of pixel columns and/or pixel rows incremented or decremented by one.
As in claim 2, Peng et al discloses the display system of claim 1, further comprising a memory storing a plurality of entries indicating measured performance capabilities of the pixel panel; wherein: the plurality of entries includes an entry for a pixel grouping that includes the first pixel and the second pixel; the entry indicates the first performance capability of the first pixel and the second performance capability of the second pixel; and the first light emitted by the first pixel and the second light emitted by the second pixel are based on the entry. [0080] In some embodiments the selected subset of the image shifts or positions may be selected based on information related to the location of defective pixels of the electronic display 50. Information about the location of defective pixels of the electronic display 50 may be saved in pixel memory 85. [0081] In some embodiments the display calibration system 90 may include subframe scaling memory 97 storing pixel scaling data for the subframes.
As in claim 3, Peng et al discloses the display system of claim 2, wherein: the pixel grouping further includes a third pixel of the pixel panel, the third pixel having a third performance capability with respect to the criterion and the entry further indicating the third performance capability of the third pixel; the operations further include causing third light emitted by the third pixel to be displayed at the pixel position on the display during presentation of a third subframe of the frame; the first performance capability is more than sufficient to achieve a target performance at the pixel position; the second performance capability is at least sufficient to achieve the target performance at the pixel position; the third performance capability is less than sufficient to achieve the target performance at the pixel position; and based on the entry, the pixel controller causes the first light to be above the target performance, the second light to be at the target performance, and the third light to be below the target performance. (Par 0079 and 0080) discloses the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. Thus, if the image of one or more an active areas is to be shifted to appear at the position of a different pixel to correct or compensate for the pixel defect, the image of the active areas will be such that the combine effect will compensate the defect of the defective pixel.
As in claim 4, Peng et al discloses the display system of claim 1, wherein: an additional pixel position on the display is separate from the pixel position and is offset from a grid on which the pixel position is aligned; and the operations further include causing the first light emitted by the first pixel to be displayed at the additional pixel position during presentation of a third subframe of the frame. [0075] the ISD 60 may be configured to shift an image of the display 50, or a portion thereof, by a fraction 11 of the display pixel pitch in an image plane. The processor 70 may be configured to render a higher-resolution input image frame 71 into two or more subframes 73 of a lower resolution at offset sampling grids.
As in claim 5, Peng et al discloses the display system of claim 1, wherein: the first pixel and the second pixel are disposed on a same row or column of a grid of the pixel panel; and the pixel controller causes the first light and the second light to be displayed at the pixel position by shifting the pixel panel, with respect to the display, along a single dimension. (Fig 3 and Par 0096) discloses the optics block 55, or a portion thereof, may function as an ISD that is configured to dynamically shift an image of at least a portion of the electronic display 53 in synchronization with the electronic display 53 displaying a sequence of subframes 73
As in claim 6, Peng et al discloses the display system of claim 1, wherein: a pixel grouping in which the first pixel and the second pixel are included further includes a third pixel of the pixel panel, the third pixel having a third performance capability with respect to the criterion; the operations further include causing third light emitted by the third pixel to be displayed at the pixel position during presentation of a third subframe of the frame; the first pixel and the second pixel are disposed on a same row of a grid of the pixel panel; the first pixel and the third pixel are disposed on a same column of the grid; and the pixel controller causes the first light, the second light, and the third light to be displayed at the pixel position by shifting the pixel panel, with respect to the display, along two dimensions. (Par 0080, 0090-0092) discloses [0080] the selected subset of the image shifts or positions may be selected based on information related to the location of defective pixels of the electronic display
As in claim 7, Peng et al discloses the display system of claim 1, wherein: the first pixel and the second pixel are disposed non-contiguously on a row or column of a grid of the pixel panel; and the pixel controller causes the first light and the second light to be displayed at the pixel position by shifting the pixel panel, with respect to the display, in a manner that skips a third pixel disposed between the first pixel and the second pixel within the row or column. (Par 0080, 0090-0092) discloses [0080] the selected subset of the image shifts or positions may be selected based on information related to the location of defective pixels of the electronic display
As in claim 8, Peng et al discloses the display system of any of claim 1, wherein the criterion is pixel brightness, such that the first performance capability defines how brightly the first pixel is capable of performing and the second performance capability defines how brightly the second pixel is capable of performing. (Par 0071 and 0085) discloses a pixel defect can be emission of light at a lower light level than desired, and wherein a calibration processor 92 of the DCS 90 may be configured determine color balance at one or more pixel brightness levels based on the stored grayscale maps or pixel luminance curves for active areas of specific colors and to compute a color and/or brightness correction matrix to enable suitable color and brightness correction of one or more pixels.
As in claim 9, Peng et al discloses the display system of claim 1, wherein the criterion is pixel chromaticity, such that the first performance capability defines how close to a nominal color the first pixel is capable of achieving and the second performance capability defines how close to the nominal color the second pixel is capable of achieving. (Par 0071 and 0085) discloses a pixel defect can be emission of light at a lower light level than desired, and wherein a calibration processor 92 of the DCS 90 may be configured determine color balance at one or more pixel brightness levels based on the stored grayscale maps or pixel luminance curves for active areas of specific colors and to compute a color and/or brightness correction matrix to enable suitable color and brightness correction of one or more pixels.
As in claim 10, Peng et al discloses the display system of any of claims 1, wherein the criterion is pixel efficiency, such that the first performance capability defines how efficiently the first pixel is capable of performing and the second performance capability defines how efficiently the second pixel is capable of performing. (Par 0071 and 0085) discloses a pixel defect can be emission of light at a lower light level than desired, and wherein a calibration processor 92 of the DCS 90 may be configured determine color balance at one or more pixel brightness levels based on the stored grayscale maps or pixel luminance curves for active areas of specific colors and to compute a color and/or brightness correction matrix to enable suitable color and brightness correction of one or more pixels.
As in claim 11, Peng et al discloses the display system of any of claims 1, further comprising: an optical assembly (Fig 9 item 55) configured to transport the first light from the first pixel to the display and to transport the second light from the second pixel to the display, the optical assembly including an opto-mechanical element; and an actuator configured to displace the opto-mechanical element [(Fig 9 and Par 0095) An optics block 55, which is disposed in an optical path between the display 53 and the eye box 57, transmits image light from the display 53 to the eye box 57]; wherein the pixel controller causes the first light and the second light to be displayed at the pixel position by directing the actuator to displace the opto-mechanical element such that light emitted by the pixel panel is shifted with respect to the display. (Fig 9-11 and Par 0098-0099) discloses the display system 150 may include one or more optical devices, such as for example one or more prisms, mirrors, waveguides, and the like, that change the direction of propagation of image light 107 emitted by display 153 towards the exit pupil 157. [0099] The SD 110 may be configured to be switchable between a first state when it directs the image light in a first direction 111, and a second state when it directs the image light in a second direction 112 that differs from the first direction 111 by an angular shift θ.
As in claim 12, Peng et al discloses the display system of claims 1, further comprising: an optical assembly (Fig 9 item 55) configured to transport the first light from the first pixel to the display and to transport the second light from the second pixel to the display; and an actuator configured to displace the pixel panel [(Fig 9 and Par 0095) An optics block 55, which is disposed in an optical path between the display 53 and the eye box 57, transmits image light from the display 53 to the eye box 57]; wherein the pixel controller causes the first light and the second light to be displayed at the pixel position by directing the actuator to displace the pixel panel such that the pixel panel is shifted with respect to the optical assembly and the display. (Fig 9-11 and Par 0098-0099) discloses the display system 150 may include one or more optical devices, such as for example one or more prisms, mirrors, waveguides, and the like, that change the direction of propagation of image light 107 emitted by display 153 towards the exit pupil 157. [0099] The SD 110 may be configured to be switchable between a first state when it directs the image light in a first direction 111, and a second state when it directs the image light in a second direction 112 that differs from the first direction 111 by an angular shift θ.
As in claim 13, Peng et al discloses a method comprising: presenting, on a display of a display system (Par 0002 and Fig 4), a frame that includes a first subframe and a second subframe[[0075] the processor 70 may be configured to render a higher-resolution input image frame 71 into two or more subframes 73], wherein the display system includes the display and a pixel panel including a first pixel having a first performance capability with respect to a criterion and a second pixel having a second performance capability with respect to the criterion(Fig 2, 3 and Par 0067, 0071 & 0072) discloses [0067] FIG. 2A schematically illustrates a portion of a light emitting surface of display 10 with a 2D array of pixels 20; although only a 4×4 segment of the array is shown, a typical 2D display may include hundreds or thousands of pixels in at least one dimension. Each pixel 20 may include one or more active areas 21 which in operation emit or transmit image light, and which may include one or more subpixels. [0072] The pixelated display 50 includes an array of pixels, each pixel including one or more active areas that are configured to emit or transmit light in response to receiving image data, and interstitial spaces that may appear as dark to a viewer when ISD 60 is absent. The number of pixels in the pixel array of display 50 defines a native resolution of the display. By way of example, the pixel array of the display 50 may be a rectangular array of size N×M, with N pixel columns and M pixel rows. [0071] A second pixel adjacent to a first pixel can be defective and has a second performance capability with respect to the first pixel in that it no longer operates or operates at a lower light level than desired; configuring the display system such that first light emitted by the first pixel is displayed at a pixel position on the display during presentation of the first subframe; and configuring the display system such that second light emitted by the second pixel is displayed at the pixel position during presentation of the second subframe. (Par 0071) discloses Image pixels 41-44 prior to the shift may be said to belong to a first subframe image, and image pixels 41a-44a after the shift may be said to belong to a second subframe image. [0079] In some embodiments the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. In such embodiments the subframes 73 may be of the same resolution as the input image frame 71, but may represent the corresponding scene or pattern sampled with a sampling offset varying by a pixel pitch of the display 50, or an integer number thereof. In some embodiments two consecutive subframes 73 may each be substantially a same input frame 71 with a counter of pixel columns and/or pixel rows incremented or decremented by one.
As in claim 14, Peng et al discloses the method of claim 13, further comprising accessing an entry from a plurality of entries stored in a memory to indicate measured performance capabilities of the pixel panel; wherein: the entry corresponds to a pixel grouping that includes the first pixel and the second pixel; the entry indicates the first performance capability of the first pixel and the second performance capability of the second pixel; and the first light emitted by the first pixel and the second light emitted by the second pixel are based on the entry. [0080] In some embodiments the selected subset of the image shifts or positions may be selected based on information related to the location of defective pixels of the electronic display 50. Information about the location of defective pixels of the electronic display 50 may be saved in pixel memory 85. [0081] In some embodiments the display calibration system 90 may include subframe scaling memory 97 storing pixel scaling data for the subframes.
As in claim 15, Peng et al discloses the method of claim 14, wherein: the pixel grouping further includes a third pixel of the pixel panel, the third pixel having a third performance capability with respect to the criterion and the entry further indicating the third performance capability of the third pixel; the method further comprises causing third light emitted by the third pixel to be displayed at the pixel position on the display during presentation of a third subframe of the frame; the first performance capability is more than sufficient to achieve a target performance at the pixel position; the second performance capability is at least sufficient to achieve the target performance at the pixel position; the third performance capability is less than sufficient to achieve the target performance at the pixel position; and based on the entry, the first light is emitted above the target performance, the second light is emitted at the target performance, and the third light is emitted below the target performance. (Par 0079 and 0080) discloses the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. Thus, if the image of one or more an active areas is to be shifted to appear at the position of a different pixel to correct or compensate pixel defect, the image of the active areas will be such that the combine effect will compensate the defect of the defective pixel.
As in claim 16, Peng et al discloses the method of claim 13, wherein the criterion is pixel brightness, such that the first performance capability defines how brightly the first pixel is capable of performing and the second performance capability defines how brightly the second pixel is capable of performing. (Par 0071 and 0085) discloses a pixel defect can be emission of light at a lower light level than desired, and wherein a calibration processor 92 of the DCS 90 may be configured determine color balance at one or more pixel brightness levels based on the stored grayscale maps or pixel luminance curves for active areas of specific colors and to compute a color and/or brightness correction matrix to enable suitable color and brightness correction of one or more pixels.
As in claim 17, Peng et al discloses the method of claim 13, wherein: the display system further includes: an optical assembly (Fig 9 item 55) configured to transport the first light from the first pixel to the display and to transport the second light from the second pixel to the display, the optical assembly including an opto-mechanical element; and an actuator configured to displace the opto-mechanical element [(Fig 9 and Par 0095) An optics block 55, which is disposed in an optical path between the display 53 and the eye box 57, transmits image light from the display 53 to the eye box 57]; and the display system is configured to cause the first light and the second light to be displayed at the pixel position by directing the actuator to displace the opto-mechanical element such that light emitted by the pixel panel is shifted with respect to the display. (Fig 9-11 and Par 0098-0099) discloses the display system 150 may include one or more optical devices, such as for example one or more prisms, mirrors, waveguides, and the like, that change the direction of propagation of image light 107 emitted by display 153 towards the exit pupil 157. [0099] The SD 110 may be configured to be switchable between a first state when it directs the image light in a first direction 111, and a second state when it directs the image light in a second direction 112 that differs from the first direction 111 by an angular shift θ.
As in claim 18, Peng et al discloses a non-transitory computer-readable medium storing instructions that, when executed, cause a pixel controller of a display system to perform a process comprising: presenting, on a display of the display system [(Par 0072 and FIG. 4) discloses a display system 25 include an electronic display 50], a frame that includes a first subframe and a second subframe [[0075] the processor 70 may be configured to render a higher-resolution input image frame 71 into two or more subframes 73], wherein the display system includes the display and a pixel panel including a first pixel having a first performance capability with respect to a criterion and a second pixel having a second performance capability with respect to the criterion; (Fig 2, 3 and Par 0067, 0071 & 0072) discloses [0067] FIG. 2A schematically illustrates a portion of a light emitting surface of display 10 with a 2D array of pixels 20; although only a 4×4 segment of the array is shown, a typical 2D display may include hundreds or thousands of pixels in at least one dimension. Each pixel 20 may include one or more active areas 21 which in operation emit or transmit image light, and which may include one or more subpixels. [0072] The pixelated display 50 includes an array of pixels, each pixel including one or more active areas that are configured to emit or transmit light in response to receiving image data, and interstitial spaces that may appear as dark to a viewer when ISD 60 is absent. The number of pixels in the pixel array of display 50 defines a native resolution of the display. By way of example, the pixel array of the display 50 may be a rectangular array of size N×M, with N pixel columns and M pixel rows. [0071] A second pixel adjacent to a first pixel can be defective and has a second performance capability with respect to the first pixel in that it no longer operates or operates at a lower light level than desired.
configuring the display system such that first light emitted by the first pixel is displayed at a pixel position on the display during presentation of the first subframe; and configuring the display system such that second light emitted by the second pixel is displayed at the pixel position during presentation of the second subframe. (Par 0071) discloses Image pixels 41-44 prior to the shift may be said to belong to a first subframe image, and image pixels 41a-44a after the shift may be said to belong to a second subframe image. [0079] In some embodiments the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. In such embodiments the subframes 73 may be of the same resolution as the input image frame 71, but may represent the corresponding scene or pattern sampled with a sampling offset varying by a pixel pitch of the display 50, or an integer number thereof. In some embodiments two consecutive subframes 73 may each be substantially a same input frame 71 with a counter of pixel columns and/or pixel rows incremented or decremented by one.
As in claim 19, Peng et al discloses the non-transitory computer-readable medium of claim 18, wherein: the process further comprises accessing an entry from a plurality of data entries stored in a memory to indicate measured performance capabilities of the pixel panel; the entry corresponds to a pixel grouping that includes the first pixel and the second pixel; the entry indicates the first performance capability of the first pixel and the second performance capability of the second pixel; and the first light emitted by the first pixel and the second light emitted by the second pixel are based on the entry. [0080] In some embodiments the selected subset of the image shifts or positions may be selected based on information related to the location of defective pixels of the electronic display 50. Information about the location of defective pixels of the electronic display 50 may be saved in pixel memory 85. [0081] In some embodiments the display calibration system 90 may include subframe scaling memory 97 storing pixel scaling data for the subframes.
As in claim 20, Peng et al discloses the non-transitory computer-readable medium of claim 19, wherein: the pixel grouping further includes a third pixel of the pixel panel, the third pixel having a third performance capability with respect to the criterion and the entry further indicating the third performance capability of the third pixel; the process further comprises causing third light emitted by the third pixel to be displayed at the pixel position on the display during presentation of a third subframe of the frame; the first performance capability is more than sufficient to achieve a target performance at the pixel position; the second performance capability is at least sufficient to achieve the target performance at the pixel position; the third performance capability is less than sufficient to achieve the target performance at the pixel position; and based on the entry, the pixel controller causes the first light to be above the target performance, the second light to be at the target performance, and the third light to be below the target performance. (Par 0079 and 0080) discloses the ISD 60 may be configured so that at least some of the n virtual pixels produced by the ISD 60 from one display pixel overlap with at least some of the n virtual pixels associated with an adjacent display pixel, thereby enabling pixel redundancy and correction. This may include placing an image of an active area of a pixel of the electronic display 50, termed herein “image pixel”, into a position of an image of another active area prior to the shift. In operation the ISD 60 may shift the image of at least a portion of the display 50 between two or more of the n image positions so as to periodically place an image of a working pixel into the position of an image of a defective pixel in a preceding subframe, thereby correcting for, or at least reducing, the pixel defects. Thus, if the image of one or more an active area is to be shifted to appear at the position of a different pixel to correct or compensate pixel defect, the image of the active areas will be such that the combine effect will compensate the defect of the defective pixel.
Conclusion
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/BENYAM KETEMA/Primary Examiner, Art Unit 2626
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