DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a transistor” twice. It is unclear as to whether the second recitation of “a transistor” refers to the first or is a separate transistor. Additionally, it is unclear as to which “a transistor” the limitation “the transistor” refers to. Thus, claim 1 is indefinite.
Claims 2-19 are rejected by virtue of their dependency from claim 1.
Claim 16 recites the limitation “the control” in line 1. There is no antecedent basis for this limitation in the claims. Thus, claim 16 is indefinite.
Claim 19 recites the limitation “at least one control device” in line 1. There is no antecedent basis for this limitation in the claims. Additionally, claim 19 recites the limitation “the at least one device” in lines 2-3. There is no antecedent basis for this limitation in the claims. Thus, claim 19 is indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 15, 16, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horiguchi et al (US PGPUB 2023/0261653).
Regarding claim 1 as best understood, Figure 6 of Horiguchi discloses a control circuit [80, 300, and 400] for a transistor [1], wherein the control circuit is configured to be coupled to a transistor [1] and to lower a voltage applied to a gate of the transistor when a current delivered to the gate is higher than a first threshold for a first time period [paragraphs 88-95].
Regarding claim 2 as best understood, Figure 6 of Horiguchi discloses wherein the control circuit is configured to keep the voltage applied to the gate lowered for a second time period [paragraphs 88-95].
Regarding claim 3 as best understood, Figure 6 of Horiguchi discloses wherein the voltage applied to the gate of the transistor is lowered so that the transistor changes conduction state [paragraphs 88-95].
Regarding claim 15 as best understood, Figure 6 of Horiguchi discloses where the current delivered to the gate is higher than a first threshold continuously for a first time period [paragraphs 88-95].
Regarding claim 16 as best understood, Figure 6 of Horiguchi discloses a control device comprising at least one of the control and at least one transistor so that the control circuit is coupled to the gate of the transistor [80].
Regarding claim 20, Figure 6 of Horiguchi discloses a transistor control method comprising: lowering of a voltage applied to a gate of a transistor [1] by a control circuit of the transistor [80, 300, and 400] when a current delivered to the gate is higher than a first threshold for a first time period [paragraphs 88-95].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-7, 14, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Horiguchi et al (US PGPUB 2023/0261653).
Regarding claim 4 as best understood, Horiguchi does not explicitly disclose wherein the first threshold is greater than or equal to 100 µA.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a threshold of greater than or equal to 100 µA as a matter of simple design-choice, since it has been held that where the general conditions of a claim are disclosed in the prior art, finding the optimum or workable ranges only involves routine skill in the art.
Regarding claim 5 as best understood, Figure 6 of Horiguchi, as applied to claim 4, discloses wherein the first threshold is greater than or equal to 400 µA [see rejection of claim 4].
Regarding claim 6 as best understood, Horiguchi does not explicitly disclose wherein the first time period is equal to or greater than 100 nanoseconds.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a time period of equal or greater than 100 nanoseconds as a matter of simple design-choice, since it has been held that where the general conditions of a claim are disclosed in the prior art, finding the optimum or workable ranges only involves routine skill in the art.
Regarding claim 7 as best understood, Horiguchi does not explicitly disclose wherein the second time period is equal to or greater than 200 nanoseconds.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a time period of equal or greater than 200 nanoseconds as a matter of simple design-choice, since it has been held that where the general conditions of a claim are disclosed in the prior art, finding the optimum or workable ranges only involves routine skill in the art.
Regarding claim 14 as best understood, Horiguchi does not explicitly disclose wherein a second terminal of a first switch is coupled to an output node of the control circuit via a resistor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a resistor for coupling as a matter of simple design-choice, since it was well-known in the art to use coupling resistors to condition signals.
Regarding claim 17 as best understood, Horiguchi does not explicitly disclose wherein the transistor is a high electron mobility transistor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a HEMT as a matter of simple design-choice, since it was well-known in the art to use HEMTs in power circuits.
Regarding claim 18 as best understood, Horiguchi does not explicitly disclose wherein the transistor is based on a GaN alloy.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using a GaN alloy as a matter of simple design-choice, since it was well-known in the art to use GaN alloys in power transistors.
Regarding claim 19 as best understood, Horiguchi does not explicitly disclose a system comprising a motor and at least one control device, wherein the motor is controlled by the at least one device.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Horiguchi by using it to control a motor as a matter of simple design-choice, since it was well-known in the art to use power transistors to control motors.
Allowable Subject Matter
Claims 8-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
Prosecution Insights