Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the Applicant’s disclosure does not explicitly define the computer-readable storage medium. Therefore, Examiner broadly construes the medium to include both tangible embodiments and intangible embodiments. As such, the claim is not limited to statutory subject matter and is therefore non-statutory.
NOTE: A claim drawn to such a computer readable medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 101 by adding the limitation “non-transitory” to the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9, 10, 12 and 18 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ramsey et al. (US Pub. No. 2016035217), hereinafter referred to as Ramsey in view of Fujimoto (US Pat. No. 8533521), and further view of Lee et al. (US Pat. No. 6735709), hereinafter referred to as Lee.
As to claim 1, Ramsey discloses a method for training a serial peripheral interface (SPI) controller (Ramsey discloses SPI controller 100, Fig. 1, paras. 0021-0024), the method comprising:
training (Ramsey discloses iteratively calibrating SPI controller 100 by testing phase-offset values and identifying a tuning-range window, Figs. 1 and 3, paras. 0035-0043) the SPI controller (Ramsey discloses SPI controller 100, Fig. 1, paras. 0021-0024).
Fujimoto discloses, what Ramsey lacks, generating (Fujimoto discloses DLL 41 generating phase-shifted sampling clocks, Fig. 4, col. 5, ll. 8-18) a plurality of delayed clock signals (Fujimoto discloses a plurality of phase taps of DLL 41 that are out of phase with one another, Fig. 4, col. 5, ll. 8-18) based on a received clock signal (Fujimoto discloses DLL 41 receiving and adjusting the phase of the clock signal supplied by clock 23, Figs. 3-4, col. 4, ll. 58-65 and col. 5, ll. 8-18), wherein the plurality of delayed signals (Fujimoto discloses out-of-phase sampling-clock signals provided by the plurality of DLL phase taps, Fig. 4, col. 5, ll. 8-18) respectively correspond to a plurality of TAP values (Fujimoto discloses a plurality of phase-tap positions selectable by multiplexer 42 and stored in register 43, Fig. 4, col. 5, ll. 8-18) respectively indicating an amount of delay (Fujimoto discloses phase-tap positions ranging from the smallest delay to the largest delay, Figs. 4-6, col. 7, ll. 14-34) for the plurality of delayed clock signals (Fujimoto discloses sampling clocks having respective degrees of phase displacement relative to the received clock signal, Fig. 4, col. 5, ll. 8-18); and
corresponding to one of the plurality of delayed clock signals (Fujimoto discloses selecting a phase tap that provides the optimum sampling clock, Figs. 4-6, col. 5, ll. 8-18 and col. 7, ll. 25-39).
Ramsey and Fujimoto are analogous art because they are from the same problem-solving area of calibrating clock-to-data sampling timing in synchronous digital interfaces using selectable clock-delay values to compensate for propagation delay, phase misalignment, and data-capture errors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramsey and Fujimoto before him or her, to modify the SPI-controller calibration system of Ramsey to include the switchable clock frequencies and DLL-generated plurality of phase-shifted clock signals corresponding to respective selectable TAP values of Fujimoto.
The suggestion/motivation for doing so would have been to provide Ramsey’s SPI-controller calibration system with Fujimoto’s known and predictable mechanism for generating, selecting, and testing multiple delayed clock phases at selectable clock frequencies, thereby allowing the controller to identify a TAP value that reliably samples incoming data despite clock-to-data phase misalignment.
Therefore, it would have been obvious to combine Fujimoto with Ramsey to obtain the invention as specified in claim 1.
Lee further discloses, what Ramsey and Fujimoto lacks, receiving (Lee discloses receiving and correctly capturing a calibration bit pattern at logic device 101 or 103, Figs. 9A-9B, col. 5, ll. 21-52) a first data set (Lee discloses a calibration bit pattern received and stored in pattern register 127, Figs. 9A-9B, col. 5, ll. 21-39 and col. 6, ll. 15-25) at a first clock frequency (Lee discloses receiving the calibration bit pattern at a first data rate slower than the normal operating rate by reducing the frequency of the clock signal used to synchronize receipt of the pattern, Figs. 7 and 9A-9B, col. 5, ll. 40-52 and col. 6, ll. 45-59; claims 2 and 7, col. 12, ll. 28-45), wherein the first data set (Lee discloses the stored calibration bit pattern used as a reliable reference during subsequent calibration, Figs. 9A-9B, col. 5, ll. 21-39 and col. 6, ll. 15-33) includes data received (Lee discloses calibration-pattern bits received and stored at the slower clock-controlled rate, Figs. 7 and 9A-9B, col. 5, ll. 40-52 and col. 6, ll. 45-59) based on the plurality of delayed clock signals corresponding to the plurality of TAP values (Ramsey and Lee disclose receiving calibration data using different test phase-offset values and obtaining the reliable reference calibration data at the first slower clock frequency, Ramsey Figs. 1 and 3, paras. 0032 and 0039-0043; Lee Figs. 7 and 9A-9B, col. 5, ll. 40-52 and col. 6, ll. 45-59);
obtaining (Lee discloses receiving a repeating calibration signal during timing calibration of a signal path, Figs. 9A-9B and 11, col. 9, ll. 6-31) a second data set (Lee discloses the pattern of calibration bits received on the signal path under calibration, Figs. 9A-9B and 11, col. 9, ll. 6-31) at a second clock frequency (Lee discloses transmitting and receiving the calibration signal at the normal operating data rate, which is faster than the first data rate and may be four or eight times the first data rate, col. 3, ll. 1-7; claims 3-6, col. 12, ll. 31-42), wherein the second data set (Lee discloses the received calibration-signal bit pattern evaluated during calibration, Figs. 9A-9B and 11, col. 9, ll. 6-31) includes data received (Lee discloses sampling and examining the calibration signal at each adjusted delay value, Figs. 2, 4, 5, 9A-9B and 11, col. 10, ll. 19-34 and col. 11, ll. 1-20) based on the plurality of delayed clock signals corresponding to the plurality of TAP values (Lee discloses stepping through all possible delay values and sampling the calibration signal at each delay value, Figs. 4-5, col. 10, ll. 19-34 and col. 11, ll. 1-20); and
a predetermined number of iterations (Lee discloses stepping through the finite set of all possible delay values, illustrated as ten predetermined delay possibilities CLK1 through CLK10 and D1 through D10, Figs. 4-5, col. 10, ll. 19-34 and col. 11, ll. 1-47), wherein the training operation (Lee discloses a calibration operation that tests the available timing-delay values and selects an acceptable delay, Figs. 4-5 and 9A-9B, col. 10, ll. 19-34 and col. 11, ll. 1-50) comprises:
determining (Lee discloses comparing received calibration data with stored reference calibration data and recording whether the calibration pattern is properly recognized, Figs. 4-5 and 9B, col. 9, ll. 6-17 and col. 11, ll. 1-47) a plurality of pass/fail statuses (Lee discloses a logic-state pattern in which logic “1” represents proper recognition and logic “0” represents failure to recognize the calibration pattern, Fig. 5, col. 11, ll. 21-47) for the respective plurality of TAP values (Lee discloses respective delay values D1 through D10 tested by control logic circuit 21, Figs. 4-5, col. 11, ll. 21-47) by comparing (Lee discloses comparison performed by compare circuit 123, Figs. 9A-9B, col. 9, ll. 6-17) the second data set obtained at the second clock frequency (Lee discloses the calibration-signal bit pattern received at the normal operating data rate, col. 3, ll. 1-7 and col. 9, ll. 6-17) with the first data set received at the first clock frequency (Lee discloses comparison with the calibration bit pattern reliably captured and stored at the slower data rate established by reducing the clock frequency, Figs. 7 and 9A-9B, col. 5, ll. 40-52, col. 6, ll. 21-33 and 45-59, and col. 9, ll. 6-17);
setting (Lee discloses storing logic “1” when the calibration pattern is properly recognized and logic “0” when the calibration pattern is not recognized, Fig. 5, col. 11, ll. 21-47) the plurality of pass/fail statuses (Lee discloses logic-state results respectively associated with delay values D1 through D10, Figs. 4-5, col. 11, ll. 21-47) based on the comparison (Lee discloses comparing the received calibration-signal pattern with the calibration pattern stored in pattern register 127, Fig. 9B, col. 9, ll. 6-17); and
selecting (Lee discloses selecting a final delay value approximately centered within the delay values that produced proper recognition, Figs. 4-5, col. 11, ll. 14-20 and 47-50), based on the plurality of pass/fail statuses (Lee discloses selecting based on the logic-state pattern identifying passing delay values D4 through D7 and failing delay values D1 through D3 and D8 through D10, Fig. 5, col. 11, ll. 21-50), a selected TAP value (Lee discloses selecting center delay value D5 or D6 from the passing delay window, Figs. 4-5, col. 11, ll. 47-50) from the plurality of TAP values (Lee discloses testing all possible delay values using control logic circuit 21, Figs. 4-5, col. 10, ll. 19-34 and col. 11, ll. 1-20).
The Ramsey–Fujimoto combination and Lee are analogous art because they are from the same problem-solving area of calibrating clock-to-data sampling timing in synchronous digital interfaces by varying clock frequency and sampling delay to identify a reliable data-capture point.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of the Ramsey–Fujimoto combination and Lee before him or her, to modify the multiple-frequency, multiple-TAP calibration system resulting from the combination of Ramsey and Fujimoto to include Lee’s technique of first receiving and storing calibration data at a reduced clock frequency as a reliable reference dataset.
The suggestion/motivation for doing so would have been to improve the reliability of the Ramsey–Fujimoto calibration procedure by establishing a correctly captured reference dataset under a less timing-sensitive, reduced-frequency condition and using that dataset to determine which TAP values correctly capture data at the higher operating frequency.
Therefore, it would have been obvious to combine Lee with the Ramsey–Fujimoto combination to obtain the invention as specified in claim 1.
As to claim 3, the modified system of Ramsey discloses the method of claim 1, further comprising storing (Ramsey discloses that calibration-controller module 110 stores original test data containing the same test pattern as the requested predetermined test data, Fig. 1, para. 0037) the first data set (Ramsey discloses the original test data used as the reference against which the returned realigned MISO test data is compared, Fig. 1, paras. 0037 and 0040) in a non-volatile memory (Ramsey discloses that internal memory 120 may be non-volatile memory, Fig. 1, para. 0026) of the serial peripheral interface (SPI) controller (Ramsey discloses internal memory 120 as a component of SPI controller 100, Fig. 1, paras. 0021 and 0026).
As to claim 9, the modified system of Ramsey discloses the method of claim 1, further comprising repeating (Ramsey discloses performing additional iterations for the SPI slave devices intended to be calibrated and configuring the calibration operation for selected or all SPI slave devices, Fig. 1, paras. 0036–0037) the receiving operation (Ramsey discloses requesting and receiving test data from each selected SPI slave device during its calibration iteration, Fig. 1, paras. 0037–0038), the obtaining operation (Ramsey discloses obtaining the requested MISO test data from the selected SPI slave device and applying the selected test phase-offset value, Fig. 1, paras. 0038–0041) and the training operation (Ramsey discloses calibrating each selected SPI slave device using different test phase-offset values to determine and store a respective phase-offset value, Fig. 3, paras. 0036–0043) for one or more other chip selects (Ramsey discloses using a chip-select index identifying each SPI slave device and performing additional calibration iterations for other selected SPI slave devices, chip-select index module 114 and chip-select lines 138, Fig. 1, paras. 0027–0030 and 0036–0038) of the SPI controller (Ramsey discloses SPI controller 100 controlling the chip-select index module and calibrating selected or all coupled SPI slave devices, Fig. 1, paras. 0021, 0027–0030, and 0036–0038).
As to claim 10, the modified system of Ramsey discloses a serial peripheral interface (SPI) controller (Ramsey discloses SPI controller 100 configured as an SPI master device to manage communications with SPI slave devices 102, Fig. 1, paras. 0021 and 0025–0029), comprising:
a plurality of shift registers (Lee discloses pattern register 127 and four-stage shift register 151 for storing and generating calibration-pattern data, Figs. 6 and 9(B), col. 5, lines 33–65; col. 6, lines 1–33);
a comparator (Lee discloses compare circuit 123 configured to compare a received calibration bit pattern with the calibration bit pattern stored in pattern register 127, Fig. 9(B), col. 5, lines 33–39; col. 9, lines 6–17) operatively coupled to the plurality of shift registers (Lee discloses compare circuit 123 operatively coupled to pattern register 127);
a delay line circuit (Fujimoto discloses DLL 41 of sampling-clock adjustment unit 25, Fig. 4, col. 5, lines 8–18) to generate (Fujimoto discloses DLL 41 generating plural phase-shifted versions of a clock signal, Fig. 4, col. 5, lines 8–18) a plurality of delayed clock signals (Fujimoto discloses a plurality of clock signals output through respective phase taps of DLL 41, Fig. 4, col. 5, lines 8–18) based on a received clock signal (Fujimoto discloses DLL 41 receiving the clock signal supplied by clock 23 and generating the respective phase-shifted clock signals, Figs. 3–4, col. 4, lines 58–65; col. 5, lines 8–18), wherein the plurality of delayed signals (Fujimoto discloses the plural phase-shifted clock signals provided by the respective DLL phase taps, Fig. 4, col. 5, lines 8–18) respectively correspond to a plurality of TAP values (Fujimoto discloses respective selectable phase-tap positions of DLL 41, with each phase-tap position corresponding to a respective TAP value, Fig. 4, col. 5, lines 8–18) respectively indicating an amount of delay for the plurality of delayed clock signals (Fujimoto discloses that each DLL phase tap produces a clock signal displaced from the received clock signal by a corresponding degree, thereby representing a respective amount of clock delay, Fig. 4, col. 5, lines 8–18); and
a training control circuitry (Ramsey discloses calibration-controller module 110 within SPI controller 100 for controlling iterative phase-offset calibration, Fig. 1, paras. 0036–0043; Lee discloses control logic circuit 21, compare circuit 123, variable-delay circuit 27, and pattern register 127 implementing timing calibration, Fig. 9(B), col. 5, lines 33–48; col. 9, lines 6–17) to: receive (Lee discloses receiving a calibration bit pattern from calibration-pattern storage device 105 before timing calibration, Figs. 9(A)–9(B), col. 5, lines 40–52; col. 6, lines 21–33) a first data set (Lee discloses the calibration bit pattern received and stored in pattern register 127 for subsequent use as reference data by compare circuit 123, Figs. 9(A)–9(B), col. 6, lines 21–33; col. 9, lines 6–17) at a first clock frequency (Lee discloses transferring the calibration pattern at a slower data rate produced by reducing the clock frequency to assure correct capture and storage, Figs. 7 and 12, col. 6, lines 21–59; col. 9, lines 6–17), wherein the first data set includes data received (Lee discloses receiving and storing the calibration-pattern data under the reduced-frequency condition, pattern register 127, Figs. 9(A)–9(B), col. 6, lines 21–59) based on the plurality of delayed clock signals corresponding to the plurality of TAP values (Fujimoto discloses sequentially receiving tuning-pattern data while selecting among the plurality of phase-tap positions of DLL 41, such that the received data corresponds to the respective delayed sampling-clock signals and TAP values, Figs. 4–5, col. 5, lines 8–18; col. 7, lines 1–39; Lee discloses receiving the reference calibration pattern at the reduced clock frequency, Figs. 7, 9(A)–9(B), and 12, col. 6, lines 21–59); obtain (Lee discloses subsequently obtaining a calibration signal at the normal operating data rate for comparison with the stored reference calibration pattern, compare circuit 123, Figs. 9(A)–9(B), col. 6, lines 21–33; col. 9, lines 6–17) a second data set (Lee discloses the subsequently received calibration bit pattern supplied to compare circuit 123, Fig. 9(B), col. 9, lines 6–17) at a second clock frequency (two arts here: Lee discloses performing calibration at the normal operating rate after capturing the reference pattern at the slower rate, col. 6, lines 21–33; Fujimoto discloses clock 23 switchable between 25 MHz and 50 MHz, Fig. 3, col. 4, lines 58–65), wherein the second data set includes data received (Lee discloses receiving and sampling the calibration-pattern data on the signal path under calibration, control logic circuit 21 and latch 23, Figs. 2 and 9(B), col. 9, lines 6–17; col. 10, lines 50–65) based on the plurality of delayed clock signals corresponding to the plurality of TAP values (Fujimoto discloses sequentially receiving tuning-pattern data while selecting the plurality of phase-tap positions of DLL 41, thereby obtaining received data corresponding to the respective delayed sampling-clock signals and TAP values, Figs. 4–5, col. 5, lines 8–18; col. 7, lines 1–39); and
train (Ramsey discloses calibration-controller module 110 iteratively calibrating SPI communications using different test phase-offset values, Fig. 3, paras. 0040–0043) the SPI controller (Ramsey discloses calibrating SPI controller 100 to determine an operative phase-offset value for communications with a selected SPI slave device 102, Fig. 1, paras. 0035–0043) for a predetermined number of iterations (Fujimoto discloses performing a finite TAP sweep by sequentially selecting the DLL taps from the smallest-delay TAP until the minimum passing TAP is identified and from the largest-delay TAP until the maximum passing TAP is identified, whereby the number of test iterations is predetermined by the finite plurality of available phase taps, Fig. 5, col. 7, lines 1–39): determining (Lee discloses control logic circuit 21 determining whether the received calibration pattern is correctly sampled at each tested delay value, Figs. 2 and 5, col. 10, lines 19–34) a plurality of pass/fail statuses (Lee discloses storing patterns representing which tested delay values provide correct sampling and recognition of the calibration pattern, thereby indicating passing and failing delay values, Figs. 2 and 5, col. 10, lines 19–34) for the respective plurality of TAP values (Fujimoto discloses testing the tuning patterns at the respective plurality of DLL phase-tap positions and identifying the TAP positions at which the patterns are read without error, Fig. 5, col. 7, lines 1–39) by comparing (Lee discloses compare circuit 123 comparing the calibration pattern received on the signal path under calibration with the reference calibration pattern stored in pattern register 127, Fig. 9(B), col. 9, lines 6–17) the second data set obtained at the second clock frequency (Lee discloses receiving the calibration signal at the normal operating rate after storage of the reference pattern, col. 6, lines 21–33; col. 9, lines 6–17) with the first data set received at the first clock frequency (Lee discloses comparing the normal-rate calibration signal with the reference calibration pattern previously received and stored under the slower-frequency condition, pattern register 127 and compare circuit 123, Fig. 9(B), col. 6, lines 21–33; col. 9, lines 6–17);
setting (Ramsey discloses generating corresponding test-result data according to whether the comparison identifies valid data, a leading-bit error, or a trailing-bit error, calibration-controller module 110, Fig. 3, para. 0040) the plurality of pass/fail statuses (Lee discloses recording which tested delay values provide correct sampling and recognition of the calibration pattern, control logic circuit 21, Figs. 2 and 5, col. 10, lines 19–34) based on the comparison (Lee discloses determining successful or unsuccessful sampling according to whether compare circuit 123 finds a reliable match between the received calibration pattern and the stored reference pattern, Fig. 9(B), col. 9, lines 6–17); and
selecting (Fujimoto discloses selecting an optimum phase-tap position at the center of the error-free TAP range, sampling-clock adjustment unit 25, Fig. 5, col. 7, lines 1–39), based on the plurality of pass/fail statuses (Fujimoto discloses identifying the minimum and maximum phase-tap positions at which the tuning patterns are received without error and selecting the center of that passing TAP range, Fig. 5, col. 7, lines 1–39), a selected TAP value (Fujimoto discloses selecting an optimum phase-tap position and storing the selected TAP position in register 43, DLL 41, multiplexer 42, and register 43, Figs. 4–5, col. 5, lines 8–18; col. 7, lines 1–39) from the plurality of TAP values (Fujimoto discloses selecting one phase-tap position from the plurality of phase taps generated by DLL 41, multiplexer 42, Fig. 4, col. 5, lines 8–18) corresponding to one of the plurality of delayed clock signals (Fujimoto discloses that the selected DLL phase tap provides the corresponding phase-shifted sampling-clock signal, DLL 41 and multiplexer 42, Fig. 4, col. 5, lines 8–18). See claim one for the reason and motivation for the combination of Ramsey, Fujimoto and Lee to obtain the invention as specified in claim 10.
As to claim 12, the modified system of Ramsey discloses the SPI controller of claim 10, wherein the first data set (Ramsey discloses original test data containing the same test pattern as the predetermined test data requested from the selected SPI slave device, Fig. 1, para. 0037) is stored (Ramsey discloses calibration-controller module 110 storing the original test data used for comparison with the returned realigned test data, Fig. 1, paras. 0037 and 0040) in a non-volatile memory (Ramsey discloses that internal memory 120 may be non-volatile memory, Fig. 1, para. 0026) of the SPI controller (Ramsey discloses internal memory 120 as a component of SPI controller 100, Fig. 1, paras. 0021 and 0026).
As to claim 18, the modified system of Ramsey discloses the SPI controller of claim 10, wherein the training control circuitry (Ramsey discloses calibration-controller module 110 configured to control calibration of selected SPI slave devices, Fig. 1, paras. 0036–0043) is to train (Ramsey discloses calibrating the phase-offset value associated with a selected SPI slave device and performing additional calibration iterations for other SPI slave devices, Fig. 1, paras. 0036–0043) the SPI controller for a predetermined number of iterations (Ramsey discloses a first iteration and additional iterations for each SPI slave device intended to be calibrated, Fig. 1, paras. 0036–0037) for multiple chip selects (Ramsey discloses calibrating selected or all SPI slave devices identified by respective chip-select indices and controlled through corresponding chip-select lines, chip-select index module 114 and chip-select lines 138–144, Fig. 1, paras. 0027–0030 and 0036–0038) of the SPI controller (Ramsey discloses chip-select index module 114 and the corresponding chip-select lines as components controlled by SPI controller 100, Fig. 1, paras. 0021 and 0027–0030).
Claim 19 recites the corresponding limitation of claim 1. Therefore, they are rejected accordingly.
Allowable Subject Matter
Claims 2, 4 – 8, 11 and 13 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hung et al. (US Pub. No. 20230046642) disclosed a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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