DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 04/03/2025 are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20220269419 A1) in view of KIM et al (US 20170110165 A1), herein KIM2.
As per claim 1, KIM teaches a memory system comprising:
a memory device (The host device 50 may include a memory controller that controls an operation of the memory device 100, or may function as the memory controller. For example, the host device 50 may control data write/read operations performed by the memory device ; KIM p. 0037) configured to store first training information and second training information representing different training patterns (the training operation may be performed using a first training pattern having the first condition, and the second training pattern having the second condition in order to perform the read DQ calibration operation. Here, the first training pattern and second training pattern may be stored in the memory device 101 (e.g., in a mode register, see, e.g., the mode register; KIM p. 0081)
and a memory controller configured to (a memory controller that controls an operation of the memory device; KIM p. 0037):
perform a first training operation on the memory device based on the first training information, perform a verify operation of verifying a result of the first training operation when the result of the first training operation is out of a predetermined range (the training operation (S200) may include; a first training operation performed on the first data I/O pin PDQ02 providing the first data signal DQ0 using the first training pattern and the second training pattern (step S210); p. 0083), and perform a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation (once the first training operation has been successfully completed, the training pattern(s) set in the mode register may be (but need not always be) respectively changed from the first training pattern and the second training pattern to some other training pattern used during a subsequent training operation; Kim p. 0085).
For KIM patterns may be changed for a subsequent operation but not choosing between the first and second information based on the verification results. Therefore, KIM does not explicitly teach perform a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation.
However, KIM2 in an analogous art teaches perform a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison… the first command/address signal CA1 may have a different pattern from the previous pattern of the first command/address signal CA1; KIM2 p. 0091).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM with the teachings of KIM2 by configuring a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ choosing between the first and second information based on the verification results in the system of KIM because KIM2 teaches a memory device and system supporting command bus training having improved accuracy (KIM2 p. 0004).
As per claim 2, KIM in view of KIM2, as combined above, teaches the memory system of claim 1,
wherein the memory controller is configured to perform the verify operation by re-performing the first training operation on the memory device based on the first training information and by checking whether a result of the re-performed first training operation is out of the predetermined range (a training status may be checked after the first training operation is performed…when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed. Thus, the first training operation may be repeatedly until the first training operation is successfully completed; KIM p. 0084)(The command/address comparator 270a may compare the first command/address signal CA1 stored in the command/address register 240a with the second command/address signal CA2 received from the memory device 100a through the data input/output circuit 260a. The command/address comparator 270a may output a pass/fail signal PF according to a result of comparing the first command/address signal CA1 with the second command/address signal; KIM2 p. 0069).
As per claim 3, KIM in view of KIM2, as combined, teaches the memory system of claim 2,
wherein the memory controller is configured to perform, when it is checked that the result of the first training operation is out of the predetermined range, according to the verify operation, the second training operation on the memory device based onthe second training information (the first command/address signal CA1 may have a different pattern from the previous first command/address signal CA1; Kim2 p. 0085).
As per claim 4, KIM in view of KIM2, as combined, teaches the memory system of claim 3,
wherein the memory controller is further configured to repeat performing the second training operation and compute accumulated training data for a number of repetitions (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison…When the command bus training is not ended, the memory controller 200a may repeat to transmit the first command/address signal in operation; KIM2 p. 0085).
As per claim 5, KIM in view of KIM2, as combined, teaches the memory system of claim 4,
wherein the memory controller is further configured to compute a final training value based on a result of the second training operation, when the number of the repetitions exceeds a predetermined number (the memory controller 200a may determine whether the delay of the first command/address signal CA1 is adjusted to a maximum value (or a minimum value) which is adjustable. Alternatively, the memory controller 200a may determine whether the delay of the first command/address signal CA1 may be determined based on the accumulated results of the comparison…The memory controller 200a may determine the delay of the first command/address signal CA1 based on the accumulated results of the comparison in operation…the memory controller 200a may select the delay of the first command/address signal CA1 corresponding to a median of the first command/address signal CA1 pass window; KIM2 p. 0091-0092).
As per claim 9, KIM teaches a memory system comprising:
a memory device (The host device 50 may include a memory controller that controls an operation of the memory device 100, or may function as the memory controller. For example, the host device 50 may control data write/read operations performed by the memory device ; KIM p. 0037) configured to store plurality of training information representing different training patterns (the training operation may be performed using a first training pattern having the first condition, and the second training pattern having the second condition in order to perform the read DQ calibration operation. Here, the first training pattern and second training pattern may be stored in the memory device 101 (e.g., in a mode register, see, e.g., the mode register; KIM p. 0081).
and a memory controller (a memory controller that controls an operation of the memory device; KIM p. 0037) configured to perform training operations based on the different training patterns (the training operation (S200) may include; a first training operation performed on the first data I/O pin PDQ02 providing the first data signal DQ0 using the first training pattern and the second training pattern (step S210); p. 0083);
wherein the memory controller configured to perform a verify operation to determine whether a noise in a result of the training operations is continued to change the different training patterns (a training status may be checked after the first training operation is performed. When the training status corresponds to a PASS result, it may be readily determined that the first training operation was successfully completed, and the result of the first training operation may be stored. However, when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed. Thus, the first training operation may be repeatedly until the first training operation is successfully completed (PASS/FAIL criterion equates predetermined range); KIM p. 0084).
For KIM patterns may be changed for a subsequent operation but not choosing between the first and second information based on the verification results. Therefore, KIM does not explicitly teach wherein the memory controller configured to perform a verify operation to determine whether a noise in a result of the training operations is continued to change the different training patterns.
However, KIM2 in an analogous art wherein the memory controller configured to perform a verify operation to determine whether a noise in a result of the training operations is continued to change the different training patterns (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison… the first command/address signal CA1 may have a different pattern from the previous pattern of the first command/address signal CA1; KIM2 p. 0091).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM with the teachings of KIM2 by configuring a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ choosing between the first and second information based on the verification results in the system of KIM because KIM2 teaches a memory device and system supporting command bus training having improved accuracy (KIM2 p. 0004).
As per claim 17, KIM teaches a method of operating a memory system (The host device 50 may include a memory controller that controls an operation of the memory device 100, or may function as the memory controller. For example, the host device 50 may control data write/read operations performed by the memory device ; KIM p. 0037), the method comprising:
performing a first training operation on a memory device based on first training information (the training operation (S200) may include; a first training operation performed on the first data I/O pin PDQ02 providing the first data signal DQ0 using the first training pattern and the second training pattern (step S210); p. 0083);
performing a verify operation of verifying a result of the first training operation when the result of the first training operation is out of a predetermined range (a training status may be checked after the first training operation is performed. When the training status corresponds to a PASS result, it may be readily determined that the first training operation was successfully completed, and the result of the first training operation may be stored. However, when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed. Thus, the first training operation may be repeatedly until the first training operation is successfully completed (PASS/FAIL criterion equates predetermined range); KIM p. 0084),
and performing a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation (once the first training operation has been successfully completed, the training pattern(s) set in the mode register may be (but need not always be) respectively changed from the first training pattern and the second training pattern to some other training pattern used during a subsequent training operation; Kim p. 0085).
For KIM patterns may be changed for a subsequent operation but not choosing between the first and second information based on the verification results. Therefore, KIM does not explicitly teach performing a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation.
However, KIM2 in an analogous art teaches performing a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison… the first command/address signal CA1 may have a different pattern from the previous pattern of the first command/address signal CA1; KIM2 p. 0091).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM with the teachings of KIM2 by configuring a second training operation on the memory device based on the first training information or the second training information according to a result of the verify operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ choosing between the first and second information based on the verification results in the system of KIM because KIM2 teaches a memory device and system supporting command bus training having improved accuracy (KIM2 p. 0004).
As per claim 18, KIM in view of KIM2, as combined, teaches the method of claim 17, the performing the verifying operation includes:
re-performing the first training operation on the memory device based on the first training information; and checking whether a result of the re-performed first training operation is out of the predetermined range (a training status may be checked after the first training operation is performed…when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed. Thus, the first training operation may be repeatedly until the first training operation is successfully completed; KIM p. 0084)(The command/address comparator 270a may compare the first command/address signal CA1 stored in the command/address register 240a with the second command/address signal CA2 received from the memory device 100a through the data input/output circuit 260a. The command/address comparator 270a may output a pass/fail signal PF according to a result of comparing the first command/address signal CA1 with the second command/address signal; KIM2 p. 0069).
As per claim 19, KIM in view of KIM2, as combined, teaches the method of claim 18, further comprising
performing, when it is checked that the result of the first training operation is out of the predetermined range, according to the verify operation, the second training operation on the memory device based on the second training information (the first command/address signal CA1 may have a different pattern from the previous first command/address signal CA1; Kim2 p. 0085).
Claims 6-7, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of KIM2 in further view of KOSTINSKY et al (US 20140189224 A1), herein KOSTINSKY.
As per claim 6, KIM in view of KIM2, as combined, teaches the memory system of claim 2. The combination does not explicitly teach claim 6.
However, KOSTINSKY in an analogous art teaches wherein the memory controller performs, when it is checked that the result of the first training operation belongs within the predetermined range, according to the verify operation, the second training operation on the memory device based on the first training information (The pattern results are compared, 760, to determine whether the current timing parameters have passed, 765, or failed, 770…if each pattern results in four `1` bits received and the signatures for the two patterns are different, the pattern training has passed…When the results indicate a pass, the CA_ModeSucceeded is marked TRUE; KOSTINSKY p. 0056-0057)(Set CLK, CS, CA delay values (loop)…if ==4--continue e. Transmit pattern B…if ==4 and signature is different from A's--mark as passing point; KOSTINSKY p. 0059-0079).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM in view of KIM2 with the teachings of KOSTINSKY by configuring performing the second training operation on the memory device based on the first training information.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing the second operation based on the first information in the system of KIM in view of KIM2 because KOSTINSKY teaches before any other memory device training steps can begin, the MRC must make sure the Control signals are aligned at all the memory (e.g., DRAM) devices, so all the issued commands register correctly (KOSTINSKY p. 0033).
As per claim 7, KIM in view of KIM2 in further view of KOSTINSKY, as combined, teaches the memory system of claim 1,
wherein the memory device is configured to compute a final training value based on the result of the first training operation when the result of the first training operation belongs within the predetermined range (obtaining an optimal value based on the first training operation result and the second training operation result; KIM Claim 20)(The pattern results are compared, 650, to determine whether the current timing parameters have passed, 655, or failed…the results comparison involves checking the number of `1` bits received for each training pattern…if each pattern results in four `1` bits received and the signatures for the two patterns are different, the pattern training has passed; KOSTINSKY p. 0052)(Decide on optimal delay point to be located in the middle of the largest passing points region; KOSTINSKY p. 0081).
As per claim 14, KIM in view of KIM2 in further view of KOSTINSKY, as combined, teaches the memory system of claim 9,
wherein the memory controller is configured to change, in response to determining that the noise is continued, the first training pattern to a second training pattern represented by second training information to re-perform the second training operation (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison. The memory controller 200a may determine whether to end the command bus training in operation S110…When the command bus training is not ended, the memory controller 200a may repeat to transmit the first command/address signal in operation…the first command/address signal CA1 may have a different pattern from the previous first command/address signal CA1; Kim2 p. 0085), and re-perform, in response to determining that the noise is not continued, the second training operation based on the first training pattern (The pattern results are compared, 760, to determine whether the current timing parameters have passed, 765, or failed, 770…if each pattern results in four `1` bits received and the signatures for the two patterns are different, the pattern training has passed…When the results indicate a pass, the CA_ModeSucceeded is marked TRUE; KOSTINSKY p. 0056-0057)(Set CLK, CS, CA delay values (loop)…if ==4--continue e. Transmit pattern B…if ==4 and signature is different from A's--mark as passing point; KOSTINSKY p. 0059-0079).
As per claim 15, KIM in view of KIM2 in further view of KOSTINSKY, as combined, teaches the memory system of claim 14,
wherein the memory controlleris further configured to repeat performing the second training operation and compute accumulated training data for a number of repetitions (The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison…When the command bus training is not ended, the memory controller 200a may repeat to transmit the first command/address signal in operation; KIM2 p. 0085).
As per claim 16, KIM in view of KIM2 in further view of KOSTINSKY, as combined, teaches the memory system of claim 15,
wherein the memory controller is further configured to compute a final training value based on a result of the second training operation, when the number of the repetitions exceeds a predetermined number (the memory controller 200a may determine whether the delay of the first command/address signal CA1 is adjusted to a maximum value (or a minimum value) which is adjustable. Alternatively, the memory controller 200a may determine whether the delay of the first command/address signal CA1 may be determined based on the accumulated results of the comparison…The memory controller 200a may determine the delay of the first command/address signal CA1 based on the accumulated results of the comparison in operation…the memory controller 200a may select the delay of the first command/address signal CA1 corresponding to a median of the first command/address signal CA1 pass window; KIM2 p. 0091-0092).
As per claim 20, KIM in view of KIM2 in further view of KOSTINSKY, as combined, teaches the method of claim 19, further comprising
computing a final training value based on the result of the first training operation when the result of the first training operation belongs within the predetermined range (obtaining an optimal value based on the first training operation result and the second training operation result; KIM Claim 20)(The pattern results are compared, 650, to determine whether the current timing parameters have passed, 655, or failed…the results comparison involves checking the number of `1` bits received for each training pattern…if each pattern results in four `1` bits received and the signatures for the two patterns are different, the pattern training has passed; KOSTINSKY p. 0052)(Decide on optimal delay point to be located in the middle of the largest passing points region; KOSTINSKY p. 0081)..
Claims 8 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of KIM2 in further view of Srebranig (US 20100169247 A1).
As per claim 8, KIM in view of KIM2 in further view of Srebranig, as combined, teaches the memory system of claim 1. The combination does not explicitly teach claim 8.
However, Srebranig in an analogous art teaches wherein the predetermined range is a range within value of standard deviation in a standard distribution data acquired from the first training information (The bin demarcations are defined by the .sigma. derived from the entire data set (the whole population), that is, the standard deviation of the curve 140; Srebranig p. 0023)(calculate a mean (.mu.) and standard deviation (.sigma.) for the initial data…3.sigma. control limits are calculated for the initial data; Srebranig p. 0029)(A Gaussian (or normal) distribution is described by a mean (represented by p) and a standard deviation (represented by a); Srebranig p. 0021).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM in view of KIM2 with the teachings of Srebranig by make the predetermined range a range within value of standard deviation in a standard distribution data acquired from the first training information.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ standard deviation in a standard distribution data in the system of KIM in view of KIM2 because Srebranig teaches methods of a macro-analytical plan to serve in a micro-analytical realm and generates increasingly narrow accuracy with statistical assurance (Srebranig p. 0036).
As per claim 10, KIM in view of KIM2 in further view of Srebranig, as combined, teaches the memory system of claim 9,
wherein the memory controller is further configured to determine presence of the noise by comparing a result of a first training operation with training reference data (a training status may be checked after the first training operation is performed…When the training status corresponds to a PASS result, it may be readily determined that the first training operation was successfully completed…when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed.; KIM p. 0084) (The controller 402 obtains a plurality of training values via the input interface 404 and calculates a population mean and a population standard deviation from the plurality of training values…defines the histogram bins A through N from the population mean and the population standard deviation; Srebranig p. 0039)(The information is the signal and what is not information, but is added into the measurement with the signal, is noise…a measurement system is required to estimate a signal in the presence of noise; Srebranig p. 0004).
wherein the first training operation is performed based on first training pattern included in first training information (the training operation may be performed using a first training pattern having the first condition, and the second training pattern having the second condition in order to perform the read DQ calibration operation. Here, the first training pattern and second training pattern may be stored in the memory device… the memory device 101 may load DQ calibration patterns (or read patterns) including the first training pattern and the second training pattern, and may store (or set) the DQ calibration patterns in the mode register…a first training operation performed on the first data I/O pin PDQ02 providing the first data signal DQ0 using the first training pattern and the second training pattern; KIM p. 0081-0083), and
wherein the training reference data is acquired based on the first training information (A process 300 according to the present disclosure performs a training sequence in step 302 to gather initial data (for example, 100 data points) and calculate a mean (.mu.) and standard deviation (.sigma.) for the initial data…From this information, in step 304 3.sigma. control limits are calculated for the initial data. In step 306, the process 300 calculates bins and confidence intervals for the bins; Srebranig p. 0029).
As per claim 11, KIM in view of KIM2 in further view of Srebranig, as combined, teaches the memory system of claim 10,
wherein the memory controller, during the verify operation, is configured to perform, in response to determining that the noise exists, a second training operation based on the first training pattern; and determine whether a result of the second training operation is out of a predetermined range (a training status may be checked after the first training operation is performed…when the training status corresponds to a FAIL result, it may be readily determined that the first training operation was not successfully completed. Thus, the first training operation may be repeatedly until the first training operation is successfully completed; KIM p. 0084)(The command/address comparator 270a may compare the first command/address signal CA1 stored in the command/address register 240a with the second command/address signal CA2 received from the memory device 100a through the data input/output circuit 260a. The command/address comparator 270a may output a pass/fail signal PF according to a result of comparing the first command/address signal CA1 with the second command/address signal; KIM2 p. 0069).
As per claim 12, KIM in view of KIM2 in further view of Srebranig, as combined, teaches the memory system of claim 11,
wherein the predetermined range is a range within value of standard deviation(a) in a standard distribution data acquired from the first training information (The bin demarcations are defined by the .sigma. derived from the entire data set (the whole population), that is, the standard deviation of the curve 140; Srebranig p. 0023)(calculate a mean (.mu.) and standard deviation (.sigma.) for the initial data…3.sigma. control limits are calculated for the initial data; Srebranig p. 0029)(A Gaussian (or normal) distribution is described by a mean (represented by p) and a standard deviation (represented by a); Srebranig p. 0021).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of KIM2 in further view of Srebranig in further view of KOSTINSKY
As per claim 13, KIM in view of KIM2 in further view of Srebranig, as combined, teaches the memory system of claim 11,
wherein the memory controller is configured to (see Fig. [0000] col. line):
determine, in response to determining that the result of the second training operation is out of the predetermined range, the noise is continued (The command/address comparator 270a may compare the first command/address signal CA1 stored in the command/address register 240a with the second command/address signal CA2 received from the memory device 100a through the data input/output circuit 260a. The command/address comparator 270a may output a pass/fail signal PF according to a result of comparing the first command/address signal CA1 with the second command/address signal; KIM2 p. 0069)(The memory controller 200a may compare the first command/address signal CA1 with the second command/address signal CA2 in operation S109, and may accumulate results of the comparison. The memory controller 200a may determine whether to end the command bus training in operation S110…When the command bus training is not ended, the memory controller 200a may repeat to transmit the first command/address signal in operation…the first command/address signal CA1 may have a different pattern from the previous first command/address signal CA1; Kim2 p. 0085).
The combination does not explicitly teach determine, in response to determining that the result of the second training operation is within the predetermined range, the noise is not continued.
However, KOSTINSKY in an analogous art teaches determine, in response to determining that the result of the second training operation is within the predetermined range, the noise is not continued (The pattern results are compared, 760, to determine whether the current timing parameters have passed, 765, or failed, 770…if each pattern results in four `1` bits received and the signatures for the two patterns are different, the pattern training has passed…When the results indicate a pass, the CA_ModeSucceeded is marked TRUE; KOSTINSKY p. 0056-0057)(Set CLK, CS, CA delay values (loop)…if ==4--continue e. Transmit pattern B…if ==4 and signature is different from A's--mark as passing point; KOSTINSKY p. 0059-0079).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM in view of KIM2 in further view of Srebranig with the teachings of KOSTINSKY by configuring performing the second training operation on the memory device based on the first training information.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing the second operation based on the first information in the system of KIM in view of KIM2 in further view of Srebranig because KOSTINSKY teaches before any other memory device training steps can begin, the MRC must make sure the Control signals are aligned at all the memory (e.g., DRAM) devices, so all the issued commands register correctly (KOSTINSKY p. 0033).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
PARK BUM SEOK (KR 20200095684 A) teaches a semiconductor device, and more particularly, to a controller, a memory system and an operation method thereof. According to an embodiment of the present invention, the controller for controlling the operation of a memory device including a plurality of data storage areas comprises: a storage area allocation module that allocates a data storage area to store write data among a plurality of data storage areas; a data storage reliability determination module that determines the data storage reliability of the allocated data storage area based on process information of the memory device; a parity management module that generates parity for the write data based on the determined data storage reliability; and a control signal generation module that generates a control signal for controlling the memory device to store the write data and parity data in the allocated data storage area.
Breed (US 20050046584 A1) teaches wirelessly controlling systems in an asset, such as a house or trailer, in which a movable device, such as a PDA, cellular telephone or vehicle, includes a transmitter arranged to transmit signals, and a control unit is arranged on or in connection with the asset and includes a receiver which communicates with the transmitter and a processor coupled to the receiver and which generates different command signals based on signals generated by the transmitter and received by the receiver. Each system is arranged on or in connection with the asset and coupled to the control unit and is responsive to command signals from the processor to perform a function relating to or affecting the asset.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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