CTNF 19/169,588 CTNF 89829 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Warnes (US PGPUB 2020/0177087) . Regarding claim 1, Figure 3 of Warnes discloses a driver circuit for controlling a high-power switch [Q1], the driver circuit comprising: a flyback converter [101], comprising a positive output rail [131], which is configured to provide a positive output voltage with reference to a ground terminal [GROUND; 132; paragraph 50] a negative output rail [133], which is configured to provide a negative output voltage with reference to the ground terminal [GROUND; 132; paragraph 50] a driving stage that is connected between the positive output rail and the negative output rail [U1] wherein the driving stage is configured to provide a high-power switch control signal for controlling the state of the high-power switch [Q1; paragraphs 75-91] a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value [102; paragraphs 75-91] wherein the shunt regulator is powered by the positive output voltage on the positive output rail [131] a short-circuit transistor having a conduction channel that is connected between the negative output rail and the ground terminal, and a control terminal [Q2] a regulation control circuit configured to provide a short-circuit control signal to the control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold [102; paragraphs 75-91] Regarding claim 2, Figure 3 of Warnes discloses wherein the positive threshold is sufficient for powering the shunt regulator [paragraphs 75-91] . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3-7 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Warnes 1 (US PGPUB 2020/0177087) in view of Warnes 2 (US PGPUB 2022/0149835) . Regarding claim 3, Warnes 1 does not explicitly disclose wherein the shunt regulator comprises an error amplifier, which is configured to compare the negative output voltage to the target negative voltage value, and wherein the error amplifier is powered by the positive output voltage on the positive output rail. Figure 8 of Warnes 2 discloses wherein the shunt regulator comprises an error amplifier [812], which is configured to compare the negative output voltage to the target negative voltage value [812], and wherein the error amplifier is powered by the positive output voltage on the positive output rail [850]. Accordingly, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to have included an error amplifier as taught by Warnes 2 in the circuit of Warnes 1 for the purpose of supplying the positive and negative output voltages. Regarding claim 4, the combination of Warnes 1 and Warnes 2, as applied to claim 3, discloses wherein: the shunt regulator further comprises a shunt transistor, wherein the shunt transistor comprises: a conduction channel that is connected between the negative output rail and the ground terminal; and a control terminal; and the error amplifier circuit is configured to provide a shunt control signal to the control terminal of the shunt transistor, wherein the shunt control signal is representative of the difference between a reference voltage and the negative output voltage [814 Figure 8 Warnes 2]. Regarding claim 5, the combination of Warnes 1 and Warnes 2, as applied to claim 4, discloses wherein: the shunt transistor is configured to operate in an ohmic mode, having a variable ohmic value that depends on the shunt control signal; and the short-circuit transistor is configured to operate in a low ohmic mode [Figure 3 Warnes 1; Figure 8 Warnes 2]. Regarding claim 6, the combination of Warnes 1 and Warnes 2, as applied to claim 5, does not explicitly disclose wherein the shunt transistor and the short-circuit transistor are implemented as a single transistor [814 Figure 8 Warnes 2]. Regarding claim 7, the combination of Warnes 1 and Warnes 2, as applied to claim 6, discloses wherein the single transistor is configured to operate in a low ohmic mode when it receives the short control signal, and is configured to operate in a variable ohmic mode when it receives the shunt control signal [814 Figure 8 Warnes 2]. Regarding claim 11, Warnes 1 does not explicitly disclose wherein the regulation control circuit further comprises a current mirror, wherein the current mirror comprises: a first branch, which includes a resistor in series with the conduction channel of a first internal disable transistor; a second branch, which includes the conduction channel of a second internal disable transistor; wherein: the first branch is connected between the positive output rail and the negative output rail; the second branch is connected between the positive output rail and the negative output rail; the conduction channel of the second internal disable transistor is connected between the control terminal of the short-circuit transistor and the negative output rail; the first and the second internal disable transistors are configured to receive an internal disable signal; and the time constant of the first branch is less than the time constant of the second branch. Figure 7 of Warnes 2 discloses wherein the regulation control circuit further comprises a current mirror [712], wherein the current mirror comprises: a first branch, which includes a resistor [716] in series with the conduction channel of a first internal disable transistor [720]; a second branch, which includes the conduction channel of a second internal disable transistor [722]; wherein: the first branch is connected between the positive output rail and the negative output rail [750 and 760]; the second branch is connected between the positive output rail and the negative output rail [750 and 760]. Accordingly, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to have included a current mirror as taught by Warnes 2 in the circuit of Warnes 1 for the purpose of supplying the positive and negative output voltages . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 8-10 and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TOMI SKIBINSKI/Primary Examiner, Art Unit 2836 Application/Control Number: 19/169,588 Page 2 Art Unit: 2836 Application/Control Number: 19/169,588 Page 3 Art Unit: 2836 Application/Control Number: 19/169,588 Page 4 Art Unit: 2836 Application/Control Number: 19/169,588 Page 5 Art Unit: 2836 Application/Control Number: 19/169,588 Page 6 Art Unit: 2836 Application/Control Number: 19/169,588 Page 7 Art Unit: 2836 Application/Control Number: 19/169,588 Page 8 Art Unit: 2836
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