DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 1-20-2000 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 103
Claims 12 to 13 and 18 to 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (USPAP 2024/0411699).
Claim 12:
Kim teaches a system, an apparatus and a method for reducing power consumption in memory operations, the apparatus comprising: a memory device mapping an input address for a large memory to each memory macro’s corresponding to the address (see par. 0049). Kim teaches that the memory device includes bipartite-parking address mappers for determining if an input address falls within a mapped address range (see par. 0052). Kim teaches that the input address is a logical address (“first format”) prior to address encoding (see par. 0033). Kim teaches that the input address changes across memory macros to maintain a Hamming distance that is smaller than the corresponding macro’s address bus width (see par. 0058).
Kim teaches that in response to determining that the input address is lower than the first address range mapped to the first memory macro, the first bipartite-parking address mapper prevents access to the first memory macro with the address bus if the first memory macro parked at a first mapped address corresponding to a lowest logical input address in the first address range mapped to the first memory macro (see par. 0070). Kim teaches that power consumption may be reduced by utilizing bipartite-parking address mappers to prevent access to corresponding memory macros and to keep their addresses mapped to a particular value, when an input address is not within an address range of a memory macro (see par. 0077). Kim further teaches that different encoding methods can be applied within the memory macro to further reduce toggling (see par. 0078).
Kim teaches that the memory device considers different toggling rates and different per-toggle power for different pins that do not experience the same power consumption wherein, in a two-bank memory macro, power consumption of a pin corresponding to an MSB is about 1/5 of an LSB (see par. 0080 et seq.). Kim teaches that address mapping may include encoding the least-significant n bits of the write address bus and corresponding encoding of least-significant n bits (LSB) of the read address bus (see par. 0084). Kim also teaches that partial Gray coding reduces LSB toggling frequency in half at the cost of an exclusive-OR gate for each memory macro’s address buses; which, reads on “ a first monitor component configured to determine a respective difference between: a number of toggles associated with access using the respective first plurality of sets of address bits having the first format” (see par. 0087).
Kim fails to specifically teach the claimed invention of: “a number of toggles associated with access using the respective first plurality of sets of address bits with the respective portion of each set of the respective first plurality of sets of address bits having the second format;” however, this teaching is obvious to the teachings of Kim since, Kim teaches that various encoding methods can be applied within a memory macro to reduce toggling and applying a Gray coding scheme for the memory macro address to reduce LSB toggling frequency (see par. 0085 and 0087).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to include the limitation of: “a number of toggles associated with access using the respective first plurality of sets of address bits with the respective portion of each set of the respective first plurality of sets of address bits having the second format;” because Kim teaches that reducing power consumption when accessing a memory is dependent on reducing toggling frequency and providing a method for reducing toggling frequency includes processing memory macros where input data are mapped to the memory macros. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for reducing power consumption and lowering the toggling rate when accessing a memory as taught by Kim (see par. 0006).
As per claim 13, Kim teaches multiple bipartite parking-address mappers (201, 202 & 203) mapping input data to multiple memory macro’s (204, 205 and 206) wherein different input addresses are mapped respectively from the bipartite-parked address mapper (see par. 0052 et seq). Kim teaches input addresses from decimal 8 (5’b01000) to decimal 13 (5’b01101), the second macro (205) is accessed with mapped addresses from decimal 0 (3’b000) to decimal 5 (3’b101) (see par. 0056).
As per claim 18, Kim teaches that the memory device includes multiple bipartite-parking address mappers to determine if an input address falls within a mapped address range corresponding to the respective memory macros (see par. 0052 et seq.). Kim teaches that the address bus has 5 bits, and the memory macros has 3 bits (see par. 0051).
As per claim 19, Kim teaches that memory access for the macro memory is an incremental pattern, which reads on “wherein respective binary values of two sets of address bits of the first plurality of sets of address bits differ in a single bit position (see par. 0065).
As per claim 20, Kim teaches applying a partial Gray code (“reflected binary code (RBC format”) encoding in a subset of address busses (see par. 0085).
Allowable Subject Matter
Claims 14 to 17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1 to 11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record teaches a method and an apparatus for address mapping for reduction of power consumption with toggling as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “receiving one or more results respectively corresponding to comparisons, wherein each comparison corresponds to a respective one of a plurality of configurations and is between a respective first number of toggles and a respective second number of toggles, wherein: the respective second number of toggles is associated with access the respective memory location using the respective plurality of sets of address bits with a first portion of the respective plurality of sets of address bits having a second format.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (USPAP 2006/0242329) discloses a power efficient encoder.
Benson, Richard Clive, (GB 2 366 635 A) discloses a Gray code program counter and address complier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
