Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2- 21 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1 - 20 of U.S. Patent No. US116307789. Although the claims at issue are not identical, they are not patentably distinct from each other because both the present application and the related patent teach the management of the latency of interrupt requests and indicating if the interrupt was assigned in a certain time interval. The related patent gives a detailed embodiment of the scaled interrupt system, while the present application is focused on the control circuit that monitors and signals the acknowledgement signals. One of ordinary skill in the art would have detected the functionality of the controller in both interrupt systems as illustrated in the table below.
Present Application
US11630789
2. A processor comprising: one or more subsystem circuits; and a control circuit coupled to the one or more subsystem circuits and configured to: generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the one or more subsystem circuits will reach an interruptible point within a specified period of time; and generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time.
15. A processor comprising: a reorder buffer configured to track a plurality of instruction operations corresponding to instructions fetched by the processor and not retired by the processor; a load/store unit configured to execute load/store operations; and a control circuit coupled to the reorder buffer and the load/store unit, wherein the control circuit is configured to generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the reorder buffer will retire instruction operations to an interruptible point and the load/store unit will complete load/store operations to the interruptible point within a specified period of time, and wherein the control circuit is configured to generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the reorder buffer and the load/store unit will not reach the interruptible point within the specified period of time.
9. A method comprising: receiving, by a processor, a particular interrupt request; determining whether one or more subsystem circuits in the processor will reach an interruptible point within a specified period of time; and based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time, generating, by a control circuit in the processor, non-acknowledge (Nack) response to the particular interrupt request.
15. A processor comprising: a reorder buffer configured to track a plurality of instruction operations corresponding to instructions fetched by the processor and not retired by the processor; a load/store unit configured to execute load/store operations; and a control circuit coupled to the reorder buffer and the load/store unit, wherein the control circuit is configured to generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the reorder buffer will retire instruction operations to an interruptible point and the load/store unit will complete load/store operations to the interruptible point within a specified period of time, and wherein the control circuit is configured to generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the reorder buffer and the load/store unit will not reach the interruptible point within the specified period of time.
16. A system comprising: a plurality of processors included in a processor cluster; and a cluster interrupt controller, coupled to the plurality of processors, that is configured to: receive an interrupt request; and send the interrupt request to a given processor of the plurality of processors; wherein the given processor is configured to: determine whether one or more subsystem circuits in the given processor will reach an interruptible point within a specified period of time; and based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time, generate a non-acknowledge (Nack) response to the interrupt request.
15. A processor comprising: a reorder buffer configured to track a plurality of instruction operations corresponding to instructions fetched by the processor and not retired by the processor; a load/store unit configured to execute load/store operations; and a control circuit coupled to the reorder buffer and the load/store unit, wherein the control circuit is configured to generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the reorder buffer will retire instruction operations to an interruptible point and the load/store unit will complete load/store operations to the interruptible point within a specified period of time, and wherein the control circuit is configured to generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the reorder buffer and the load/store unit will not reach the interruptible point within the specified period of time.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 9, 15 - 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wolfe (US20100274941).
As to claim 1, Wolfe discloses a processor comprising: one or more subsystem circuits (Fig. 2 comprising a multiprocessor system, 110); and a control circuit (Fig. 2, and controller 220) coupled to the one or more subsystem circuits and configured to: generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the one or more subsystem circuits will reach an interruptible point within a specified period of time (Fig.5 , where the interrupt controller issues a request in step 540, and during the time of timer 320 receives availability from the core, and determining the granted core in step 570, paras. 0051 – 0053); and generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time (Fig. 5, where the occupied cores reject the message, para. 0052).
As to claim 9, Wolfe discloses a method comprising: receiving, by a processor, a particular interrupt request (Fig. 2, where an interrupt from peripheral 246 is transmitted to controller 220 for processing, para 0024); determining whether one or more subsystem circuits in the processor will reach an interruptible point within a specified period of time (Fig.5 , where the interrupt controller issues a request in step 540, and during the time of timer 320 receives availability from the core, and determining the granted core in step 570, paras. 0051 – 0053); and based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time, generating, by a control circuit in the processor, non-acknowledge (Nack) response to the particular interrupt request (Fig. 5, where the occupied cores reject the request message, para. 0052).
As to claim 16, Wolfe discloses a system comprising: a plurality of processors included in a processor cluster (Fig. 2, with cluster comprising cores, 210a, .. 210e); and a cluster interrupt controller, coupled to the plurality of processors, that is configured to: receive an interrupt request (Fig. 2, with interrupt controller 220 receiving interrupts via 225); the interrupt request to a given processor (Fig. 5, and step 510) of the plurality of processors (para. 0049); wherein the given processor is configured to: determine whether one or more subsystem circuits in the given processor will reach an interruptible point within a specified period of time (Fig.5 , where the interrupt controller issues a request in step 540, and during the time of timer 320 receives availability from the core, and determining the granted core in step 570, paras. 0051 – 0053); and based on a determination that at least one of the one or more subsystem circuits will fail to reach the interruptible point within the specified period of time, generate a non-acknowledge (Nack) response to the interrupt request (Fig. 5, where the occupied cores reject the request message, para. 0052).
As to claim 15, Wolfe discloses the method further comprising: receiving, by the processor, a different interrupt request (Fig. 2, and para. 0024 where a separate and different request is transmitted); and generating, by the control circuit, an acknowledge (Ack) response to the different interrupt request based on a determination that the one or more subsystem circuits in the processor will reach an interruptible point within a different specified period of time (Fig.5 , where the interrupt controller issues a request in step 540, and during the time of timer 320 receives availability from the core, and determining the granted core in step 570, paras. 0051 – 0053).
As to claim 17, Wolfe discloses the system, wherein the given processor is further configured to generate an acknowledge (Ack) response to the interrupt request based on a determination that the one or more subsystem circuits will reach an interruptible point within the specified period of time (Fig.5 , where the interrupt controller issues a request in step 540, and during the time of timer 320 receives availability from the core, and determining the granted core in step 570, paras. 0051 – 0053).
As to claim 18, Wolfe discloses the system, wherein the cluster interrupt controller is further configured to: based on receiving the Nack response from the given processor, send the interrupt request to a second one of the plurality of processors (Fig. 5, where the occupied cores reject the request message, para. 0052).
As to claim 19, Wolfe discloses the system of claim, wherein the cluster interrupt controller is further configured to: based on receiving respective Nack responses from the plurality of processors, respond to the interrupt request with a Nack response (Fig. 5, where the occupied cores reject the request message, para. 0052).
Allowable Subject Matter
Claims 3- 8, 10- 14, and 20, 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20140115198, US7054975, and 8612660 teach interrupt latency management.
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/C.A.D/ Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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