DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 4/3/2025.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Information Disclosure Statement
The information disclosure statements (IDSes) submitted on 5/6/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…perform, based at least in part on one or more commands from a host, one or more logical operations on data stored in the one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and store results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device” (independent claim 1, lines 5-11).
The recitation of “the results” lacks antecedent basis. In addition, the Examiner is uncertain if “a host device” refers to “a host” or to a device that is a component of “a host.”
For the sake of examination, the Examiner has interpreted “…perform, based at least in part on one or more commands from a host, one or more logical operations on data stored in the one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and store results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device” to read “…perform, based at least in part on one or more commands from a host, one or more logical operations on data stored in the one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and store results of the one or more logical operations without transferring the results of the one or more logical operations via an input/output (I/O) interface to the host.”
Dependent claims 2-7, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 8 recites “…performing, based at least in part on one or more commands from a host, one or more logical operations on data stored in one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and storing results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device” (independent claim 8, lines 2-8).
The recitation of “the results” lacks antecedent basis. In addition, the Examiner is uncertain if “a host device” refers to “a host” or to a device that is a component of “a host.”
For the sake of examination, the Examiner has interpreted “…performing, based at least in part on one or more commands from a host, one or more logical operations on data stored in one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and storing results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device” to read “…performing, based at least in part on one or more commands from a host, one or more logical operations on data stored in one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and storing results of the one or more logical operations without transferring the results of the one or more logical operations via an input/output (I/O) interface to the host.”
Dependent claims 9-14, which ultimately depend from independent claim 8, are rejected for carrying the same deficiencies.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 15 recites “…store results of the one or more arithmetic operations without transferring the results via an input/output (I/O) interface to the host” (independent claim 15, lines 11-12).
The recitation of “the results” lacks antecedent basis.
For the sake of examination, the Examiner has interpreted “…store results of the one or more arithmetic operations without transferring the results via an input/output (I/O) interface to the host” to read “…store results of the one or more arithmetic operations without transferring the results of the one or more arithmetic operations via an input/output (I/O) interface to the host.”
Dependent claims 16-20, which ultimately depend from independent claim 15, are rejected for carrying the same deficiency.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 8, and 15 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 15 of U.S. Patent No. 12,277,067 (“Lea”). The following tables, in which similarities between claims 1, 8, and 15 of the instant application and claims 1, 9, and 15 of Lea are highlighted in bold, and accompany reasoning show that claims 1, 8, and 15 of the instant application are not patentably distinct from claims 1, 9, and 15 of Lea:
Instant Application, Independent Claim 1
Lea, Independent Claim 1
1. A device, comprising: one or more memory banks; and one or more compute components associated with the one or more memory banks, the one or more compute components configured to: perform, based at least in part on one or more commands from a host, one or more logical operations on data stored in the one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and store results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device.
1. An apparatus, comprising: an array of memory cells; sensing circuitry coupled to the array of memory cells; and one or more compute components included in the array, the one or more compute components configured to: perform a number of operations based at least in part on a physical address of a portion of data stored in the array, wherein the one or more compute components are configured to perform the number of operations in response to a command from a host, the command comprising an indication of the physical address associated with the portion of the data stored in the array; use the physical address as an input to a table to obtain at least one result of the number of operations, wherein the table is associated with the array, and wherein the at least one result comprises a result of a respective logical operation; and store the at least one result of the number of operations without transferring the at least one result outside the array.
The Examiner notes that the claim recitation of “[a] device” of independent claim 1 of the instant application is by definition an apparatus, as recited in independent claim 1 of Lea.
While Lea does not appear to explicitly claim that “the operations” (i.e., “the logical operations”) are arithmetic operations, the Examiner notes that the apparatus of independent claim 1 of Lea performs operations on physical addresses of memory. Such operations are necessarily arithmetic operations that use the physical addresses of memory.
Instant Application, Independent Claim 8
Lea, Independent Claim 9
8. A method, comprising: performing, based at least in part on one or more commands from a host, one or more logical operations on data stored in one or more memory banks, wherein the one or more logical operations are based at least in part on a physical address of the data stored in the one or more memory banks, and wherein the one or more logical operations comprise arithmetic operations on the data stored in the one or more memory banks; and storing results of the one or more logical operations without transferring the results via an input/output (I/O) interface to a host device.
9. A method, comprising: receiving, from a host device, a command comprising an indication of a physical address associated with data stored in an array of memory cells; performing, by one or more compute components that are included in the array of memory cells, one or more operations in response to the command from the host device, wherein the one or more operations are performed based at least in part on the physical address associated with the data; generating respective results of the one or more operations based at least in part on using the physical address as an input to a table associated with the array, each of the respective results comprising a result of a logical operation; and storing the respective results of the one or more operations without transferring the respective results outside the array.
While Lea does not appear to explicitly claim that “the operations” (i.e., “the logical operations”) are arithmetic operations, the Examiner notes that the apparatus of independent claim 1 of Lea performs operations on physical addresses of memory. Such operations are necessarily arithmetic operations that use the physical addresses of memory.
Instant Application, Independent Claim 15
Lea, Independent Claim 15
15. A memory system, comprising: a host; one or more banks of memory cells; and one or more compute components coupled with the one or more banks of memory cells, the one or more compute components configured to: receive one or more commands from the host; perform one or more arithmetic operations on data stored in the one or more banks of memory cells based at least in part on the one or more commands, wherein the one or more arithmetic operations are based at least in part on a physical address of the data stored in the one or more banks of memory cells; and store results of the one or more arithmetic operations without transferring the results via an input/output (I/O) interface to the host.
15. An apparatus, comprising: an array of memory cells; sensing circuitry coupled to the array of memory cells; one or more compute components included in the array; and a controller coupled to the one or more compute components and configured to control the one or more compute components to: in response to a command from a host, perform a number of logical operations based at least in part on a physical address of a portion of data stored in the array, the command comprising an indication of the physical address associated with the portion of the data, wherein the one or more compute components are configured to use the physical address as an input to a table to obtain at least one result of the number of logical operations, wherein the table is associated with the array, and wherein the at least one result comprises a result of a respective logical operation; and store the at least one result of the number of logical operations without transferring the at least one result outside the array.
The Examiner notes that independent claim 15 of the instant application claims “[a] memory system,” but independent claim 15 of Lea claims an apparatus that comprises memory units. The apparatus of independent claim 15 of Lea is thus “[a] memory system.”
While Lea does not appear to explicitly claim that “the operations” (i.e., “the logical operations”) are arithmetic operations, the Examiner notes that the apparatus of independent claim 15 of Lea performs operations on physical addresses of memory. Such operations are necessarily arithmetic operations that use the physical addresses of memory.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
U.S. Patent No. 6,912,644: teaches redirecting memory access requests for virtual memory to physical memory locations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
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