DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/08/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a1/a2) as being anticipated by Matsukizono, (WO 2016195039 A1,machine translastion,2016).
Regarding claim 1, Matsukizono discloses (Figures 1-16 and corresponding context) An (Figure 1A) active matrix substrate (1001)including a plurality of pixel regions (Pix) arrayed in a matrix shape (π33-π34), the active matrix substrate (1001) comprising: a substrate (1); a TFT (101) supported on the substrate (1) and provided corresponding to each of the plurality of pixel regions (Pix) (π39),, the TFT (101) including a semiconductor layer (7), a gate electrode(3), a gate insulating film (5), a source electrode (8)and a drain electrode (9), and an interlayer film(11) (π45); a plurality of gate wiring lines(G) formed from the same conductive film as the gate electrode(π40-π41), and extending in a row direction; and a plurality of source wiring lines(S)(π41) formed from the same conductive film as the source electrode and the drain electrode(π41), and extending in a column direction, wherein a light transmitting portion (800)(π48) is provided, the TFT, the gate wiring line, and the source wiring line not being disposed at the light transmitting portion(π35), the interlayer film includes a silicon nitride layer formed of silicon nitride and a silicon oxide layer formed of silicon oxide, and the interlayer film includes a first portion at the light transmitting portion, the first portion not including the silicon nitride layer(π84-π85).
Regarding claim 7, Matsukizono discloses a liquid crystal display device Figure 4a (2001), comprising: the active matrix substrate (1001) according to claim 1 (see rejection claim 1); a counter substrate(950) disposed facing the active matrix substrate(1001); and a liquid crystal layer (930) provided between the active matrix substrate (1001)and the counter substrate(950).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Matsukizono, (WO 2016195039 A1,machine translastion,2016).
Regarding claims 2-6, the limitations wherein, in the interlayer film, the silicon nitride layer is located on a lower layer side close to the semiconductor layer, and the first portion does not include the silicon oxide layer(claim 2);wherein, in the interlayer film, the silicon oxide layer is located on a lower layer side close to the semiconductor layer, and the first portion includes the silicon oxide layer.(claim 3); wherein the first portion is formed in a first region, the first region not including a portion at which the gate wiring line and the TFT are located, and the source wiring line is located on the first portion (claim 4);wherein the first portion is formed over an entire surface, excepting a lower side of the source electrode and the drain electrode, and of the source wiring line (claim5); a flattening film covering the TFT; and a pixel electrode portion provided on the flattening film and electrically connected to the TFT, wherein the pixel electrode portion includes a first pixel electrode, a second pixel electrode, an upper insulating film provided between the first pixel electrode and the second pixel electrode and formed of silicon nitride, and a second portion provided in a region in which a pixel capacitance is not formed by the first pixel electrode and the second pixel electrode, the upper insulating film not being provided at the second portion (claim 6) does not appear to contain any additional features which define more than slight constructional changes which come within the scope of the customary (design) practice followed by persons skilled in the art, especially as the advantages thus achieved can be readily contemplated in advance. Alternatively, these limitations are not deemed patentable since the applicant’s disclosure fails to show such limitations to solve any problems or to yield any unobvious advantage that is not within the scope of the teachings applied such limitations would be a matter of design alternative.
In figure 7a-7b, Matsukizono discloses an interlayer insulating layer 11 is formed so as to cover the source wiring layer and the oxide semiconductor layer 7. The interlayer insulating layer 11 may be provided with an opening that exposes the pixel electrode 15 in the display region 800. In the non-display region 900, the interlayer insulating layer 11 and the gate insulating layer 5 are provided with a first opening CH1 exposing the gate wiring G, and the interlayer insulating layer 11 is provided with a second opening CH2 exposing the source wiring S. Form As the interlayer insulating layer 11, a silicon oxide (SiO .sub.2 ) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x> y) film, a silicon nitride oxide (SiNxOy; x> y) film, or a laminated film thereof is used as a way to process the nitride layer of the interlayer film. (π80-π89).
Therefore it would be obvious to one of ordinary skill before the effective filing date to modify the display substrate of Matsukizono as discussed by Matsukizono to derive wherein, in the interlayer film, the silicon nitride layer is located on a lower layer side close to the semiconductor layer, and the first portion does not include the silicon oxide layer; wherein, in the interlayer film, the silicon oxide layer is located on a lower layer side close to the semiconductor layer, and the first portion includes the silicon oxide layer; wherein the first portion is formed in a first region, the first region not including a portion at which the gate wiring line and the TFT are located, and the source wiring line is located on the first portion ;wherein the first portion is formed over an entire surface, excepting a lower side of the source electrode and the drain electrode, and of the source wiring line; a flattening film covering the TFT; and a pixel electrode portion provided on the flattening film and electrically connected to the TFT, wherein the pixel electrode portion includes a first pixel electrode, a second pixel electrode, an upper insulating film provided between the first pixel electrode and the second pixel electrode and formed of silicon nitride, and a second portion provided in a region in which a pixel capacitance is not formed by the first pixel electrode and the second pixel electrode, the upper insulating film not being provided at the second portion the motivation being to achieve both the reduction in resistance of the wiring provided in the region and improved light transmittance, and since design alternative requires only routine skill.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsukizono, (WO 2016195039 A1,machine translastion,2016) in view of Huang et al. (US 6291255 B1) (
Huang, hereafter).
Regarding claim 8, Matsukizono discloses (Figures 1-16 and corresponding context) An (Figure 1A) active matrix substrate (1001)including a plurality of pixel regions (Pix) arrayed in a matrix shape (π33-π34), the active matrix substrate (1001) comprising: a substrate (1); a TFT (101) supported on the substrate (1) and provided corresponding to each of the plurality of pixel regions (Pix) (π39),, the TFT (101) including a semiconductor layer (7), a gate electrode(3), a gate insulating film (5), a source electrode (8)and a drain electrode (9), and an interlayer film(11) (π45); a plurality of gate wiring lines(G) formed from the same conductive film as the gate electrode(π40-π41), and extending in a row direction; and a plurality of source wiring lines(S)(π41) formed from the same conductive film as the source electrode and the drain electrode(π41), and extending in a column direction, wherein a light transmitting portion (800)(π48) is provided, the TFT, the gate wiring line, and the source wiring line not being disposed at the light transmitting portion(π35). the method comprising interlayer film forming of forming an interlayer film (11) covering the gate electrode and the gate wiring line (23), the interlayer film including a silicon nitride layer formed of silicon nitride and a silicon oxide layer formed of silicon oxide(π85-π89).
Matsukizono fails to disclose wherein hydrogenating of repairing defects in the semiconductor layer, using hydrogen supplied from the silicon nitride layer; and inorganic film removing of, subsequent to the hydrogenating, removing the silicon nitride layer in at least a part of the interlayer film located at the light transmitting portion, to form a removed region, the silicon nitride layer not being present in a film thickness direction in the removed region.
Huang discloses (Figures 1-5, columns 1-6) A method for fabricating a TFT (Thin Film Transistor) comprising:
forming a first conductive layer on a transparent substrate; patterning said first conductive layer to form a first conductive pattern on said transparent substrate; forming a first insulating layer on said first conductive pattern and said exposed transparent substrate; forming a second conductive layer on said first insulating layer; patterning said second conductive layer to form a second conductive pattern on said first insulating layer, said second conductive pattern being positioned over the first conductive pattern; forming a second insulating layer on said second conductive pattern and said exposed first insulating layer; forming a third insulating layer on said second insulating layer; baking ( hydrogenation process) said first conductive pattern, said first insulating layer, said second conductive pattern, said second insulating layer, and said third insulating layer; etching a portion of said third insulating layer, a portion of said second insulating layer, and a portion of said first insulating layer to form a first contact hole and a second contact hole in said third insulating layer, said second insulating layer, and said first insulating layer as well as to expose a first portion of said first conductive pattern and a second portion of said first conductive pattern, said first contact hole and said second contact hole being positioned at both ends of said first conductive pattern; forming a third conductive layer in said first contact hole, in said second contact hole, and said third insulating layer; patterning said third conductive layer to form a source conductive pattern and a drain conductive pattern on said third insulating layer; and etching said third insulating layer using said source conductive pattern and said drain conductive pattern as a mask until said second insulating layer is exposed to form said TFT on a TFT panel, said second conductive pattern being a gate of said TFT, said source conductive pattern and drain conductive pattern being source and drain of said TFT, transmittance of said TFT panel after etching said third insulating layer being larger than transmittance of said TFT panel before etching said third insulating layer.
Therefore it would be obvious to one of ordinary skill before the effective filing date to modify the method of Matsukizono as disclosed by Huang being motivated to drive a display of high transmittance wherein hydrogenating of repairing defects in the semiconductor layer, using hydrogen supplied from the silicon nitride layer; and inorganic film removing of, subsequent to the hydrogenating, removing the silicon nitride layer in at least a part of the interlayer film located at the light transmitting portion, to form a removed region, the silicon nitride layer not being present in a film thickness direction in the removed region.
Regarding claims 9-12, the limitations wherein source electrode forming of, subsequent to the hydrogenating, forming, on the interlayer film, the source electrode and the drain electrode, and a source wiring line electrically connected to the source electrode, using a second metal layer, wherein, in the interlayer film forming, the silicon nitride layer is formed first, and the silicon oxide layer is formed on the silicon nitride layer, and in the inorganic film removing, subsequent to the source electrode forming, at least a part of the interlayer film located at the light transmitting portion is removed to form a removed region, the interlayer film not being present in a film thickness direction in the removed region(claim 9);wherein source electrode forming of, subsequent to the hydrogenating, forming, on the interlayer film, the source electrode and the drain electrode, and a source wiring line electrically connected to the source electrode, using a second metal layer, wherein, in the interlayer film forming, the silicon oxide layer is formed first, and the silicon nitride layer is formed on the silicon oxide layer, and in the inorganic film removing, subsequent to the source electrode forming, at least a part of the silicon nitride layer located at the light transmitting portion is removed to form a removed region, the silicon nitride layer not being present in a film thickness direction in the removed region (claim 10);wherein, in the inorganic film removing, subsequent to the hydrogenating, the silicon nitride layer is removed and the silicon oxide layer is left in a first region not including a portion at which the gate wiring line and the TFT are located, and the method includes source electrode forming of forming, on the interlayer film from which the silicon nitride layer is removed, the source electrode and the drain electrode, and a source wiring line electrically connected to the source electrode, using a second metal layer (claim 11); wherein source electrode forming of, subsequent to the hydrogenating, forming, on the interlayer film, the source electrode and the drain electrode, and a source wiring line electrically connected to the source electrode, using a second metal layer, wherein, in the interlayer film forming, the silicon oxide layer is formed first, and the silicon nitride layer is formed on the silicon oxide layer, and in the inorganic film removing, subsequent to the source electrode forming, the source electrode, the drain electrode, and the source wiring line are used as a mask to remove the silicon nitride layer and leave the silicon oxide layer(claim 12) does not appear to contain any additional features which define more than slight constructional changes which come within the scope of the customary (design) practice followed by persons skilled in the art, especially as the advantages thus achieved can be readily contemplated in advance. Alternatively, these limitations are not deemed patentable since the applicant’s disclosure fails to show such limitations to solve any problems or to yield any unobvious advantage that is not within the scope of the teachings applied such limitations would be a matter of design alternative.
Therefore, it would be obvious to one of ordinary skill before the effective filing date to modify the method of Matsukizono as disclosed by Huang above to yield a display of high transmittance by varying different parameters which are not beyond the teachings of Huang , and since design alternative requires routine skill.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Can be found in the 892 provided with this document and below:
US 20220293795 A1-General state of the art- a planar transistor including an oxide semiconductor film
US 20190333461 A1-General state of the art- active-matrix substrate and particularly to an active-matrix substrate that has a configuration in which an inorganic insulating layer and organic insulating layer are stacked
US 20110025941 A1-General state of the art- active matrix substrate
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACIE Y GREEN whose telephone number is (571)270-3104. The examiner can normally be reached Mon-Thursday, 10am-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R Greece can be reached at (571)272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TRACIE Y. GREEN
Primary Examiner
Art Unit 2875
/TRACIE Y GREEN/Primary Examiner, Art Unit 2875
Prosecution Insights