DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a) regarding claim 20:
The limitation, “wherein the first switching transistor and the output compensation transistor of the electronic switching module are controlled in a staggered manner to transfer the reference voltage to the output to obtain the sampled voltage” fails to comply with the written description requirement. The specification discloses that claimed first switching transistor M5 and the claimed output compensation transistor M6 are controlled by control signals C and /C, respectively. There is no description in the specification of the claimed first switching transistor M5 and the claimed output compensation transistor M6 being controlled by staggered control signals.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6, 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a) regarding claim 4:
Claim 4 recites the limitation "the input switching transistor" in line 1. There is insufficient antecedent basis for this limitation in the claim.
b) regarding claims 5-6:
The claims are rejected based on their dependence from claim 4.
c) regarding claim 16:
Claim 16 recites the limitation "the input switching transistor" in line 1. There is insufficient antecedent basis for this limitation in the claim.
d) regarding claim 17:
The claim is rejected based on its dependence from claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12, 13, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (US Patent No. 5,019,731).
a) regarding claims 1 and 13:
Kobayashi discloses an integrated circuit comprising:
an electronic switching module (Figure 3B) including:
an input (IN) configured to receive a reference voltage (NS),
an output (OUT) configured to output a sampled voltage,
a first switching transistor (T1s) connected to the input and to the output, the first switching transistor having a channel having a first type of conductivity (column 4, lines 6-9), and
an output compensation transistor (T2) arranged between the first switching transistor (T1s) and the output (OUT), the output compensation transistor (T2) having a channel having a second type of conductivity (column 3, lines 30-31), the output compensation transistor (T2) being configured to reduce a leakage current to or from the output (column 3, lines 37-45),
wherein the first switching transistor (T1s) and the output compensation transistor (T2) are controlled by control signals (CK, XCK) to transfer the reference voltage to the output to obtain the sampled voltage (Figure 4D).
b) regarding claim 12:
Kobayashi discloses the module according to claim 1, further comprising:
a capacitive output element (C) having a first terminal connected to said output (OUTPUT) and a second terminal connected to ground.
c) regarding claim 18:
Kobayashi discloses a method for controlling an intermediate electronic switching module (Figure 3B), comprising:
driving transistors (T1s, T1m and T2) of the electronic module using control signals (CK, XCK) to transfer a reference voltage (NS) received at an input (IN) to a sampled voltage provided at an output (OUT),
wherein a first switching transistor (T1s) of the transistors is connected to the input (IN) and to the output (OUTPUT), the first switching transistor having a channel having a first type of conductivity (column 4, lines 6-9), and
an output compensation transistor (T2) of the transistors is arranged between the first switching transistor (T1s) and the output (OUTPUT), the output compensation transistor (T2) having a channel having a second type of conductivity (column 3, lines 30-31), the output compensation transistor (T2) being configured to reduce a leakage current to or from the output (column 3, lines 37-45).
d) regarding claim 19:
Kobayashi discloses the method according to claim 18, wherein the first switching transistor (T1s) and the output compensation transistor (T2) of the electronic switching module are simultaneously controlled (via XCK) to transfer the reference voltage to the output of the electronic switching module to obtain the sampled voltage (column 4, lines 11-12).
Allowable Subject Matter
Claims 2, 3, 7-11, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose or make obvious an electronic switching module, wherein: the output compensation transistor has a drain and a source configured to receive a second control signal of the control signals, wherein the second control signal is inverted with respect to the first control signal, and wherein the gate of the output compensation transistor is connected to said output, along with all the other limitations as required by claims 2 and 14.
The prior art of record fails to disclose or make obvious an electronic switching module, wherein the first switching transistor is connected to the input via an input switching transistor, the input switching transistor having a channel having said first type of conductivity, along with all the other limitations as required by claims 3 and 15.
The prior art of record fails to disclose or make obvious an electronic switching module, comprising: an intermediate compensation transistor having a channel having the second type of conductivity between the input and the first switching transistor, the intermediate compensation transistor being configured to compensate for leakage currents to or from the first switching transistor, along with all the other limitations as required by claim 7.
The prior art of record fails to disclose or make obvious an electronic switching module, comprising: at least one pair of transistors between said input and ground, the at least one pair of transistors having a node therebetween coupled to at least one sink, said at least one pair of transistors being configured to reduce a leakage current between said input and said node, along with all the other limitations as required by claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Setterberg (US 2009/0102517) discloses a track-and-hold circuit with adjustable charge compensation. Geelen (US 2006/0192546) discloses a track-and-hold circuit for use in an analog-to-digital converter.
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2836
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