DETAILED ACTION
The instant application having Application No. 19/170,663 has a total of 20 claims pending in the application; there is 1 independent claim and 19 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: apparatus in claims 1-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-2, 4, and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ohkawa (Publication Number US 2007/0106844 A1) in view of Boolos et al. (Publication Number US 2004/0015630 A1).
As per claim 1, Ohkawa discloses “An electronic apparatus comprising: a memory configured to store data for computational processing of a processor (through a shared memory 80; FIG. 2).” Ohkawa discloses “a stream input buffer configured to sequentially store input stream data that is input in a stream data format (through an input queue 20; FIG. 2; Paragraph 0053).” Ohkawa discloses “the processor, which is configured to obtain, from the memory, the input stream data in the [processor data format] (data processed by the processing unit 1 is transferred to the input queue 2. When the data is transferred from the input queue 2 to processing units 4 and 5, the identifiers of the blocks that contain the data in the input queue 2 are further added as second tags to the data which has the first tags; FIG. 14; Paragraph 0111), and store, in the memory, computational processing result data for the input stream data in the [processor data format] (when data is transferred from the processing unit 4 or 5 to the output queue 2, the second tags are referred to and the data is written to the blocks corresponding to the second tags. The data is transferred from the output queue 2 to a processing unit 3, processed by the processing unit 3, and then transferred to the output queue 1; FIG. 14; Paragraph 0111).” Ohkawa discloses “a stream output buffer configured to store the computational processing result data received from the memory in the [processor data format, convert the computational processing result data into the stream data format], and sequentially output the computational processing result data in the stream data format (FIG. 14; Paragraph 0111).” Ohkawa discloses “and a controller configured to determine a right to access the memory for the processor, the stream input buffer, and the stream output buffer, based on a state of the processor, a state of the stream input buffer and a state of the stream output buffer (see the synchronization of queues on different lines using a single notification signal; Paragraphs 0170-0172).”
Though Ohkawa discloses an identifier adding unit that adds an identifier to blocks [Paragraph 0084], Ohkawa does not disclose the processor data format as disclosed in the limitations “convert the input stream data into a processor data format that is processable by the processor, and transmit, to the memory, the input stream data in the processor data format” and “processor data format, convert the computational processing result data into the stream data format.”
Boolos et al. discloses he processor data format as disclosed in the limitation “convert the input stream data into a processor data format that is processable by the processor, and transmit, to the memory, the input stream data in the processor data format (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033).”
Boolos et al. discloses he processor data format as disclosed in the limitation “and processor data format, convert the computational processing result data into the stream data format (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033 and 0037).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ohkawa and Boolos et al. to allow all data transmissions to be compatibly processed [Paragraph 0033].
As per claim 2, Ohkawa discloses “The electronic apparatus of claim 1 (as disclosed by Ohkawa and Boolos et al. above), wherein the processor data format comprises a data word corresponding to a smallest unit processable by the processor (in the form of blocks of which the queues are divided into [Paragraph 0066]. See also atomic area of a shared memory; Paragraph 0095).”
As per claim 4, Ohkawa discloses “The electronic apparatus of claim 3 (as disclosed by Ohkawa and Boolos et al. above), wherein a size of the minimum unit buffer area is an integer multiple of a size of the data word corresponding to the smallest unit processable by the processor (in the form of blocks of which the queues are divided into [Paragraph 0066]. See also atomic area of a shared memory; Paragraph 0095)).”
As per claim 12, Ohkawa discloses “The electronic apparatus of claim 1 (as disclosed by Ohkawa and Boolos et al. above), wherein the controller is further configured to, based on receiving a request signal requesting the right to access the memory from one of the processor, the stream input buffer, or the stream output buffer, grant the right to access the memory to the one of the of the processor, the stream input buffer, or the stream output buffer that transmitted the request signal (the read pointer and the write pointer keep track of blocks of data under the constraint that they do not pass each other; Paragraph 0066).”
Claims 3, 5-11, and 13-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ohkawa (Publication Number US 2007/0106844 A1) and Boolos et al. (Publication Number US 2004/0015630 A1) in view of Guy et al. (Patent Number US 5,940,479).
As per claim 3, Ohkawa and Boolos et al. disclose “The electronic apparatus of claim 2 (as disclosed by Ohkawa and Boolos et al. above).” However, Ohkawa and Boolos et al. do not disclose “wherein each of the stream input buffer and the stream output buffer comprises a minimum unit buffer area configured to convert between the stream data format and the processor data format, and an extra buffer area.”
Guy et al. discloses “wherein each of the stream input buffer and the stream output buffer comprises a minimum unit buffer area configured to convert between the stream data format and the processor data format, and an extra buffer area (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316; Column 10, lines 53-67 to Column 11, lines 1-5).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ohkawa and Boolos et al. with elements of Guy et al. to allow for quality signals within time sensitive systems [Column 2, lines 19-63].
As per claim 5, Guy et al. discloses “the electronic apparatus of claim 3 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream input buffer is further configured to: transmit, to the controller, information indicating that the input stream data stored in the minimum unit buffer area of the stream input buffer has reached an upper limit, based on the right to access the memory being granted (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316; Column 10, lines 53-67 to Column 11, lines 1-5).”
Boolos et al. discloses “convert the input stream data stored in the minimum unit buffer area of the stream input buffer into the processor data format, and transmit the input stream data to the memory in the processor data format (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033).”
Guy et al. discloses “and based on the right to access the memory not being granted, sequentially store the input stream data in the extra buffer area of the stream input buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316; Column 10, lines 53-67 to Column 11, lines 1-5).”
As per claim 6, Guy et al. discloses “The electronic apparatus of claim 5 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream input buffer is further configured to: based on the input stream data stored in the minimum unit buffer area of the stream input buffer reaching the upper limit and the extra buffer area of the stream input buffer reaching a threshold state, transmit, to the controller, a signal to increase a priority to access the memory, and based on the right to access the memory being granted (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
Boolos et al. discloses “convert the input stream data stored in the minimum unit buffer area of the stream input buffer into the processor data format, and transmit the input stream data to the memory in the processor data format (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033).”
As per claim 7, Guy et al. discloses “The electronic apparatus of claim 6 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream input buffer is further configured to, based on the input stream data stored in the minimum unit buffer area of the stream input buffer being transmitted to the memory in the processor data format, move the input stream data stored in the extra buffer area of the stream input buffer to the minimum unit buffer area of the stream input buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316; Column 10, lines 53-67 to Column 11, lines 1-5).”
As per claim 8, Guy et al. discloses “The electronic apparatus of claim 3 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream output buffer is further configured to: transmit, to the controller, information indicating that the minimum unit buffer area and the extra buffer area of the stream output buffer are empty, based on being granted the right to access the memory, receive, from the memory, the computational processing result data in the processor data format, and store the computational processing result data in the minimum unit buffer area of the stream output buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5] indicating that the jitter buffer is used first before the overflow jitter buffer).”
As per claim 9, Guy et al. discloses “The electronic apparatus of claim 8 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream output buffer is further configured to: push the computational processing result data stored in the minimum unit buffer area of the stream output buffer into the extra buffer area of the stream output buffer, and store the computational processing result data in the minimum unit buffer area and the extra buffer area of the stream output buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5] indicating that the jitter buffer is used first before the overflow jitter buffer).”
Ohkawa discloses “and convert the computational processing result data stored in the minimum unit buffer area of the stream output buffer into the stream data format, and sequentially output the computational processing result data in the stream data format (when data is transferred from the processing unit 4 or 5 to the output queue 2, the second tags are referred to and the data is written to the blocks corresponding to the second tags. The data is transferred from the output queue 2 to a processing unit 3, processed by the processing unit 3, and then transferred to the output queue 1; FIG. 14; Paragraph 0111).”
As per claim 10, Guy et al. discloses “The electronic apparatus of claim 9 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream output buffer is further configured to: transmit, to the controller, information indicating that the minimum unit buffer area of the stream output buffer is empty, based on the right to access the memory being granted, receive, from the memory, the computational processing result data in the processor data format (Boolos et al. disclose ‘the processor data format’ [Paragraphs 0032-0033 and 0037]), and store the computational processing result data in the minimum unit buffer area of the stream output buffer, and based on the right to access the memory not being granted, convert the computational processing result data stored in the extra buffer area of the stream output buffer into the stream data format (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5] indicating that the jitter buffer is used first before the overflow jitter buffer).”
Ohkawa discloses “and sequentially output the computational processing result data in the stream data format (when data is transferred from the processing unit 4 or 5 to the output queue 2, the second tags are referred to and the data is written to the blocks corresponding to the second tags. The data is transferred from the output queue 2 to a processing unit 3, processed by the processing unit 3, and then transferred to the output queue 1; FIG. 14; Paragraph 0111).”
As per claim 11, Guy et al. discloses “The electronic apparatus of claim 10 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the stream output buffer is further configured to: based on the minimum unit buffer area of the stream output buffer being empty and the extra buffer area of the stream output buffer reaching a threshold state, transmit, to the controller, a signal to increase a priority to access the memory (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).” Boolos et al. discloses “based on the right to access the memory being granted, receive, from the memory, the computational processing result data in the processor data format (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033).” Boolos et al. discloses “and store the computational processing result data in the minimum unit buffer area of the stream output buffer (where each of the processors 40 uses a common processor protocol; Paragraphs 0032-0033).”
As per claim 13, Guy et al. discloses “The electronic apparatus of claim 12 (as disclosed by Ohkawa and Boolos et al. above), wherein the controller is further configured to, based on receiving the request signal requesting the right to access the memory from two or more of the processor, the stream input buffer, or the stream output buffer, grant the right to access the memory to one with a greatest priority to access the memory among the two or more of the processor, the stream input buffer, or the stream output buffer that transmitted the request signal (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ohkawa and Boolos et al. with elements of Guy et al. to allow for quality signals within time sensitive systems [Column 2, lines 19-63].
As per claim 14, Ohkawa and Boolos et al. disclose “The electronic apparatus of claim 12 (as disclosed by Ohkawa and Boolos et al. above).” However, Ohkawa and Boolos et al. do not disclose the priority as disclosed in the limitation “wherein the controller is further configured to, based on the stream input buffer and the stream output buffer being in a normal state, determine the processor to have a greater priority to access the memory than the stream input buffer and the stream output buffer.”
Guy et al. discloses the priority as disclosed in the limitation “wherein the controller is further configured to, based on the stream input buffer and the stream output buffer being in a normal state, determine the processor to have a greater priority to access the memory than the stream input buffer and the stream output buffer (see the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Ohkawa and Boolos et al. with elements of Guy et al. to allow for quality signals within time sensitive systems [Column 2, lines 19-63].
As per claim 15, Guy et al. discloses “The electronic apparatus of claim 13 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to, based on the stream input buffer and the stream output buffer being in a threshold state, determine a smaller of the stream input buffer or the stream output buffer to have a greater priority to access the memory (see the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
As per claim 16, Guy et al. discloses “The electronic apparatus of claim 13 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to, based on the stream input buffer being in a threshold state, determine a priority to access the memory in an order of the stream input buffer, the processor, and the stream output buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
As per claim 17, Ohkawa discloses “The electronic apparatus of claim 3 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to receive state information from each of the processor, the stream input buffer, and the stream output buffer (see the bit states for each column (initial, writing, write completed, reading, and read completed); FIG. 9).”
As per claim 18, Guy et al. discloses “The electronic apparatus of claim 17 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to, based on the input stream data stored in the minimum unit buffer area of the stream input buffer reaching an upper limit, determine, based on the state of the processor, the right to access the memory for the stream input buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
As per claim 19, Ohkawa discloses “The electronic apparatus of claim 18 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to: in a state in which the processor is accessing the memory, not grant the right to access the memory to the stream input buffer (the read pointer and the write pointer keep track of blocks of data under the constraint that they do not pass each other; Paragraph 0066).” Ohkawa discloses “and in a state in which the processor is not accessing the memory, grant the right to access the memory to the stream input buffer (the read pointer and the write pointer keep track of blocks of data under the constraint that they do not pass each other; Paragraph 0066).”
As per claim 20, Guy et al. discloses “The electronic apparatus of claim 17 (as disclosed by Ohkawa, Boolos et al., and Guy et al. above), wherein the controller is further configured to, based on the computational processing result data being stored in the extra buffer area of the stream output buffer and the minimum unit buffer area of the stream output buffer being empty, determine, based on the state of the processor, the right to access the memory for the stream output buffer (the overflow jitter buffer 424 permits data to be temporarily stored when network delay variation is larger than what can be properly handled by the jitter buffer 316 [Column 10, lines 53-67 to Column 11, lines 1-5]. See the priority management unit that controls the data priority request; Column 10, lines 53-54; Column 11, lines 36-58).”
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated April 4, 2025; October 1, 2025; and June 15, 2026, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach transmission protocols.
U.S. PATENT NUMBERS:6,665,807 B1 – [FIG. 19; Column 7, lines 21 to Column 9, line 19]
8,190,731 B2
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.W.Y/Examiner, Art Unit 2181 July 27, 2026
/Farley Abad/Primary Examiner, Art Unit 2181
Prosecution Insights