DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,2,4,5,11,12,14,15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipate by YAMAZAKI et al (US 2023/0419891).
Regarding claim 1, YAMAZAKI discloses an electronic device, comprising: a display DSP comprising a plurality of pixels PX (paragraph 11-13, 99-101); a display storage MDV comprising a plurality of pixel memories MC configured to store data voltage information so that the plurality of pixels can emit light (paragraph 11, 99-101, 133-135); a display driver DRV, comprising circuitry, configured to operate the display and the display storage (paragraph 90, 91, 134,135); a processor MFNC, comprising processing circuitry, configured to control an operation of the display driver (paragraph 96-98, 119); and a memory operatively connected to the processor, wherein the memory comprises instructions configured to cause the processor, when executed, to store the data voltage information in the display storage during one frame period and to load the stored data voltage information (paragraph 52, 143-145, 154-156; data writing and reading (storing and loading) are performed on the memory device (display storage) under the control of the processor and system components; which discloses the timing controller adjusts the frame rate, implying display operations including storing and loading image data occur on a frame basis; thus, instructions executed by the processor cause storing and loading of image data (data voltage information) in the display storage within a frame period)).
Regarding claim 2, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein the display storage comprises a plurality of first memory lines disposed in a first direction in order to form the plurality of pixel memories, a plurality of second memory lines disposed in a second direction orthogonal to the first direction, and phase change materials PCM1 disposed between the plurality of first memory lines and the plurality of second memory lines, and in the display storage, at least one pixel memory corresponding to each of the plurality of pixels is disposed (Figure 2, 4, 5F; paragraph 137-140, 177-184).
Regarding claim 4, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein the processor is configured to operate the display driver to store the data voltage information according to an emission grayscale of organic light emitting diodes (OLEDs) disposed in the plurality of pixels in the plurality of pixel memories, when storing data voltage information during a frame period (paragraph 98-101, 105-106, 113, 118, 123; EL correction).
Regarding claim 5, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein, the processor is configured to operate the display driver to load the data voltage information stored in the plurality of pixel memories, when loading data voltage information during one frame period (paragraph 98-101, 105-106, 113, 118-119).
Regarding claim 11, YAMAZAKI discloses a method of operating an electronic device (abstract), the method comprising: storing data voltage information for causing organic light emitting diodes (OLEDs) disposed in a plurality of pixels to emit light in a display storage disposed in a display during a frame period (paragraph 90, 91, 134,135); loading the data voltage information stored in the display storage during the frame period, and causing OLEDs disposed in a plurality of pixels to emit light with different grayscales in the data voltage information (paragraph 52, 143-145, 154-156).
Regarding claim 12, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein in the display storage, at least one pixel memory corresponding to each of the plurality of pixels is disposed, and the display storage stores and loads the data voltage information in at least one pixel memory corresponding to each of the plurality of pixels (paragraph 137-140, 177-184).
Regarding claim 14, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein, when storing data voltage information during the frame period, the data voltage information according to an emission grayscale of the OLEDs disposed in the plurality of pixels is stored in the plurality of pixel memories (paragraph 98-101, 105-106, 113, 118, 123; EL correction).
Regarding claim 15, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein, when loading data voltage information during the frame period, the data voltage information stored in the plurality of pixel memories is loaded (paragraph 98-101, 105-106, 113, 118-119).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3,9,10,13 is/are rejected under 35 U.S.C. 103 as being unpatentable over YAMAZAKI et al (US 2023/0419891) in view of WANG et al (US 2021/0304682).
Regarding claim 3, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. YAMAZAKI further discloses wherein a 1-bit memory is formed proximate each portion in which the plurality of first memory lines and the plurality of second memory lines intersect (Figure 5A-5G; paragraph 136-140, 183-187). However, YAMAZAKI does not expressly disclose each of the plurality of pixel memories comprises at least an 8-bit memory. In a similar field of endeavor, WANG discloses each of the plurality of pixel memories comprises at least an 8-bit memory (paragraph 49, 61, 133, 134). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of WANG, since WANG states that such a modification would allow storage of a 256 gray levels. Furthermore, the use of any memory size would be obvious to one of ordinary skill in the art based on processing needs.
Regarding claim 9, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. However, YAMAZAKI does not expressly disclose wherein the processor is configured to: store first data voltage information of a first pixel in a first pixel memory in a first frame period, and skip an operation of storing and/or loading data voltage information of the first pixel in a second frame period in a case where there is no change in data voltage information of the first pixel in the second frame period. In a similar field of endeavor, WANG discloses wherein the processor is configured to: store first data voltage information of a first pixel in a first pixel memory in a first frame period, and skip an operation of storing and/or loading data voltage information of the first pixel in a second frame period in a case where there is no change in data voltage information of the first pixel in the second frame period (paragraph 132). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of WANG, since WANG states that such a modification would allow a voltage level to be maintained when gray levels across multiple frames remain constant. Furthermore, as both inventions are analogous, such a modification would provide additional driving means based on those disclosed by WANG.
Regarding claim 10, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. However, YAMAZAKI does not expressly disclose wherein the processor is configured to: prevent an enable signal that instructs storing and/or loading of the data voltage information from being output when a first OLED disposed in the first pixel expresses black, and control to supply a driving voltage of OV to the first pixel. In a similar field of endeavor, WANG discloses wherein the processor is configured to: prevent an enable signal that instructs storing and/or loading of the data voltage information from being output when a first OLED disposed in the first pixel expresses black, and control to supply a driving voltage of OV to the first pixel (paragraph 61; no light emission corresponding to absence of driving voltage when black). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of WANG, since WANG states that such a modification would allow a voltage level to be maintained when gray levels across multiple frames remain constant. Furthermore, as both inventions are analogous, such a modification would provide additional driving means based on those disclosed by WANG.
Regarding claim 13, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. However, YAMAZAKI does not expressly disclose each of the plurality of pixel memories comprises at least an 8-bit memory. In a similar field of endeavor, WANG discloses each of the plurality of pixel memories comprises at least an 8-bit memory (paragraph 49, 61, 133, 134). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of WANG, since WANG states that such a modification would allow storage of a 256 gray levels. Furthermore, the use of any memory size would be obvious to one of ordinary skill in the art based on processing needs.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over YAMAZAKI et al (US 2023/0419891) in view of KWON (US 2009/0184901).
Regarding claim 6, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. However, YAMAZAKI does not expressly disclose wherein an analog-to-digital converter is provided and is configured so that the data voltage information loaded from the plurality of pixel memories is converted into an analog value and is supplied to the plurality of pixels. In a similar field of endeavor, KWON discloses wherein an analog-to-digital converter is provided and is configured so that the data voltage information loaded from the plurality of pixel memories is converted into an analog value and is supplied to the plurality of pixels (abstract; paragraph 19). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of KWON, since KWON states that such a modification would provide additional correction signals to be provided to a data driver. Furthermore, as both inventions are analogous, such a modification would provide additional driving means based on those disclosed by KWON.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over YAMAZAKI et al (US 2023/0419891) in view of YOSHIMOTO (US 2013/0113778).
Regarding claim 8, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. However, YAMAZAKI does not expressly disclose wherein the processor is configured to simultaneously perform an operation of storing first data voltage information of a first pixel in a first pixel memory and an operation of loading second data voltage information of a second pixel in a second pixel memory. In a similar field of endeavor, YOSHIMOTO discloses wherein the processor is configured to simultaneously perform an operation of storing first data voltage information of a first pixel in a first pixel memory and an operation of loading second data voltage information of a second pixel in a second pixel memory (paragraph 52). Therefore, it would have been obvious to a person of ordinary skill in the art to modify YAMAZAKI to include the teachings of YOSHIMOTO, since providing parallel operations is well known and conventional in the art and would provide faster response to driving a display. Furthermore, as both inventions are analogous, such a modification would provide additional driving means based on those disclosed by YOSHIMOTO.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior Art fails to disclose wherein a pixel memory including a 9-bit memory is formed by three first memory lines, three second memory lines, and phase change material disposed proximate portions in which the three first memory lines and the three second memory lines intersect, and the data voltage information for expressing 256 grayscales is to be stored in an 8-bit memory among the 9-bit memory, and a 1-bit memory is configured to be used as a parity check bit for error checking.
Conclusion
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/ARIEL A BALAOING/ Primary Examiner, Art Unit 2624