The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claims 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan (US Patent Application 20150198665) in the view of Sonawane (US Patent Application 20140189452).
As per claim 1, Srinivasan teaches a matrix circuit [100, fig. 1], comprising:
a clock circuit [105, fig. 2] configured to output a first group of output clock signals [CLK_320_SYS to CLK_80_SYS, fig. 2] and one or more additional groups of output clock signals [CLK_320_SAUX0 to CLK_80_AUX0, fig. 2], the clock circuit comprising at least one of [0016, as shown in figure 2, the cock circuits can output multiple groups of clock signals. For example, device 100 may include a clock circuit 105 configured to generate several different clock signals for use within the device 100. Such a clock circuit 105 provides one or more (often numerous) clock signals for triggering the operations of the device 10]:
at least one clock staggering circuit [410, fig. 4] configured to delay remaining output clock signals of the first group of output clock signals or the one or more additional groups of output clock signals with respect to a corresponding initial output clock signal of the first group of output clock signals or the one or more additional groups of output clock signals [0035, as shown in figure 4, the clock circuit includes multiple delay circuits that are used to delay the clock signals. For example, in the embodiment of FIG. 4, a different delay is added to the clock for each scan chain or group of scan chains. Thus, any scan chain triggered from the CLK_320_AUX0 clock signal will have a delay equivalent to one delay element 410. Similarly, any scan chain triggered from the CLK_320_AUX1 clock signal will have a delay equivalent to two delay elements 411. Likewise, any scan chain triggered from the CLK_320_AUX2 clock signal will have a delay equivalent to three delay elements 412].
Srinivasan does not teach a plurality of groups of partitions, each partition being configured to receive a different output clock signal from the first group of output clock signals or the one or more additional groups of output clock signals.
However, Sonawane teaches a plurality of groups of partitions [scan group partition figure 5], each partition being configured to receive a different output clock signal from the first group of output clock signals or the one or more additional groups of output clock signals [0068, 0070, 0083, as pointed out clock from one partition can be driven to the other partition. For example, plurality of scan chain groups in each partition and staggering the shift clock for these chains will not affect the scan load-unload operation. Also staggering within the partition can only be implemented if one or more of the scan chains in the partition can be run using a separate scan test clock from the other scan chains in the partition].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Srinivasan to include the method of Sonawane in order to group the partitions where the clock from one can drive the other ones.
As per claim 2, Srinivasan does not teach each partition of the plurality of groups of partitions is configured to perform one or more of, in response to receiving the different output clock signal, receiving a corresponding input signal or providing a corresponding output signal.
However, Sonawane teaches each partition of the plurality of groups of partitions is configured to perform one or more of, in response to receiving the different output clock signal, receiving a corresponding input signal or providing a corresponding output signal [0068, 0070, 0083, as pointed out clock from one partition can be driven to the other partition. For example, plurality of scan chain groups in each partition and staggering the shift clock for these chains will not affect the scan load-unload operation. Also staggering within the partition can only be implemented if one or more of the scan chains in the partition can be run using a separate scan test clock from the other scan chains in the partition].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Srinivasan to include the method of Sonawane in order to group the partitions where the clock from one can drive the other ones.
As per claim 5, Srinivasan teaches the clock circuit is configured to receive an input clock signal having a period [0028, 0035, periodical clock and every period. For example, if there are three scan chains, instead of a single current spike of I every period of the clock cycle, there may be 3 current spikes of 1/3 every period of the clock cycle, where these spikes are spread out from one another in time].
As per claim 7, Srinivasan teaches an output stage, wherein the clock circuit is configured to transmit an initial output clock signal of the first group of output clock signals to the output stage to trigger the output stage to transmit an output signal to an output terminal [0035, as pointed initial system clock signals feeds other system with delay the clock].
As per claim 8, Srinivasan teaches an input stage, wherein the clock circuit is configured to transmit a last signal of the one or more additional groups of output clock signals to the input stage to trigger the input stage to receive an input signal from an input terminal [0035, each group trigger signals from one input to an output].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan (US Patent Application 20150198665) in the view of Papameletis (US Patent 10775435).
As per claim 11, Sonawane teaches a system [100, fig. 1], comprising:
a clock circuit [105, fig. 2] configured to output a first group of output clock signals [CLK_320_SYS to CLK_80_SYS, fig. 2] and one or more additional groups of output clock signals [CLK_320_SAUX0 to CLK_80_AUX0, fig. 2], the clock circuit comprising at least one of [0016, as shown in figure 2, the cock circuits can output multiple groups of clock signals. For example, device 100 may include a clock circuit 105 configured to generate several different clock signals for use within the device 100. Such a clock circuit 105 provides one or more (often numerous) clock signals for triggering the operations of the device 10]:
at least one clock staggering circuit configured to delay remaining output clock signals of the first group of output clock signals or the one or more additional groups of output clock signals with respect to a corresponding initial output clock signal of the first group of output clock signals or the one or more additional groups of output clock signals [0035, as shown in figure 4, the clock circuit includes multiple delay circuits that are used to delay the clock signals. For example, in the embodiment of FIG. 4, a different delay is added to the clock for each scan chain or group of scan chains. Thus, any scan chain triggered from the CLK_320_AUX0 clock signal will have a delay equivalent to one delay element 410. Similarly, any scan chain triggered from the CLK_320_AUX1 clock signal will have a delay equivalent to two delay elements 411. Likewise, any scan chain triggered from the CLK_320_AUX2 clock signal will have a delay equivalent to three delay elements 412].
Srinivasan does not teach a measurement system configured to measure a voltage output or a current output of a plurality of groups of partitions, each partition being configured to receive a different output clock signal from the first group of output clock signals or the one or more additional groups of output clock signals.
However, Papameletis taches a measurement [circuit shown in figure 8] system configured to measure a voltage output or a current output of a plurality of groups of partitions, each partition being configured to receive a different output clock signal from the first group of output clock signals or the one or more additional groups of output clock signals [col. 4 lines 12-25, col. 6 lines 55-67, calculate the voltage of a group of partitions where partition receive clock signal from one group to another as shown in figure 6E, where clock 16 can be divided to provide clock into different clock signal to provide to different groups. As well as in figure 1, clock 105 can be divided to provide clock to different groups].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Srinivasan to include the method of Papameletis to provide a way to measure or calculate the volage for the group of partitions.
Claim 3, 9-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan (US Patent Application 20150198665) in the view of Sonawane (US Patent Application 20140189452) and in the view of Papameletis (US Patent 1077543).
As per claim 3, Srinivasan and Sonawane do not teach each partition of the plurality of groups of partitions is further configured to provide the corresponding output signal based on the corresponding input signal.
However, Papameletis teaches each partition of the plurality of groups of partitions is further configured to provide the corresponding output signal based on the corresponding input signal [col. 8 lines 1-20, as shown in figure 6E, the clock can provide output clock to different partition group from one partition to another].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Srinivasan and Sonawane to include the method of Papameletis to have the clock of the first partition feed other partitions.
As per claim 9, Srinivasan and Sonawane do not teach each partition of the plurality of groups of partitions comprises one or more sequential elements.
However, Papameletis teaches each partition of the plurality of groups of partitions comprises one or more sequential elements [col. 5 lines 26-34, for example, During the staggered clock pulse sequence, the shift enable signal 215 may be high or active. After a staggered clock pulse sequence has been performed, the shift enable signal 215 may be disabled or low, for the capture phase to be performed. This may occur using a combined pulsing of all clocks 305. After the capture phase has been performed, the staggered clock signal may be repeated with the shift register reset].
to have multiple clock signals that can be repeated.
As per claim 10, Srinivasan and Sonawane do not teach the clock circuit is further configured to output each of the first group of output clock signals and the one or more additional groups of output clock signals to a corresponding partition of the plurality of groups of partitions.
However, Papameletis teaches the clock circuit is further configured to output each of the first group of output clock signals and the one or more additional groups of output clock signals to a corresponding partition of the plurality of groups of partitions [col. 5 lines 63-67, col. 8 line 1-20, as shown in figure 6E each partition can output specific clock to separate partition groups].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Srinivasan and Sonawane to include the method of Papameletis to have multiple partition clock that can feeds other partitions.
As per claims 12-13 and 15-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 12-13 and 15-20 are also rejected as being unpatentable over Srinivasan in view of Sonawane and in the view of Papameletis for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rich (US 20030208350) teaches facilitating simulation of a model within a distributed environment.
Shelar (US 12585852) teaches multiplexing scheme for multi-clock prototyping.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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