Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 16 and 17 are objected to because of the following informalities: for both claims, “clock signal line connected with a clock signal line” should be “clock signal pad connected with a clock signal line”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5-14 and 16-20 of U.S. Patent No. 12,300,164. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter of each is corresponding.
Detailed analysis for claim 1 is provided below.
Claim 1 of Application
Patent ‘164
Comparison
A display panel, comprising: a substrate including a display area where a plurality of subpixels are disposed;
Claim 1: a display panel, comprising: a substrate including a display area where a plurality of subpixels are disposed;
Identical.
a driving circuit disposed in a non-display area outside the display area;
Claim 1: a gate driving circuit disposed in a non-display area outside the display area and supplying a plurality of scan signals to the plurality of subpixels;
Driving circuit corresponds to the gate driving circuit.
an electrostatic discharge unit, disposed in the non-display area;
Claim 1: an electrostatic discharge unit disposed in the non-display area;
Identical.
a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the driving circuit and the electrostatic discharge unit,
Claim 1: a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the gate driving circuit and the electrostatic discharge unit,
Corresponding.
wherein the plurality of pads include:
Claim 1: wherein the plurality of pads include, as sequentially disposed: a clock pad connected with a clock signal line; a first line pad connected with a first power line; an additional pad connected with an electrostatic discharge high-potential voltage line and an electrostatic discharge low-potential voltage line; and a second line pad connected with a second power line, wherein the electrostatic discharge unit protects the gate driving circuit from static charges.
an electrostatic discharge high-potential voltage pad connected with an electrostatic discharge high-potential voltage line;
an electrostatic discharge low-potential voltage pad connected with an electrostatic discharge low-potential voltage line; and at least one dummy pad positioned between the electrostatic discharge high-potential voltage pad and the electrostatic discharge low-potential voltage pad.
Claim 11: wherein the additional pad includes:
an electrostatic discharge high-potential voltage pad connected with an electrostatic discharge high-potential voltage line for transferring an electrostatic discharge high-potential voltage to the electrostatic discharge unit;
an electrostatic discharge low-potential voltage pad connected with an electrostatic discharge low-potential voltage line for transferring an electrostatic discharge low-potential voltage to the electrostatic discharge unit; and at least one dummy pad positioned between the electrostatic discharge high-potential voltage pad and the electrostatic discharge low-potential voltage pad.
Corresponding configuration of the high-potential voltage pad, low-potential voltage pad, and dummy pad(s).
As analyzed above, claim 1 of the application and claims 1 and 11 of patent ‘164 are not identical. However, the configurations of both are corresponding. Therefore, it would have been obvious to one of ordinary skill in the art to modify/simplify claims 1 and 11 of patent ‘164 as claim 1 of the application due to equivalent subject matter.
As for claim 2, gate driving circuits correspond to the gate driving circuits in claim 2 of patent ‘164.
As for claim 3, the source printed circuit and data driving circuit correspond to the same in claim 9 of patent ‘164.
As for claim 4, the clock pad of corresponds to the same in claim 1 of patent ‘164.
As for claim 5, the carry clock pad, scan clock pad, and sensing clock pad correspond to the same in claim 10 of patent ‘164.
As for claim 6, the first line pad connected to a first power line correspond to the same in claim 1 of patent ‘164.
As for claim 7, the gate high-potential voltage pad, start signal pad, reset signal pad, line selection signal pad correspond to the same in claim 5 of patent ‘164.
As for claim 8, the first gate high-potential voltage line, second gate high-potential voltage line, and third gate high-potential voltage line correspond to the same in claim 6 of patent ‘164.
As for claim 9, the 2-1th gate high-potential voltage line and 2-2th gate high-potential voltage line correspond to the same in claim 7 of patent ‘164.
As for claim 10, the first group of transistors and second group of transistors correspond to the same in claim 8 of patent ‘164.
As for claim 11, the dummy pad configuration corresponds to the same in claim 12 of patent ‘164.
As for claim 12, the electrostatic discharge unit corresponds to the same in claim 13 of patent ‘164.
As for claim 13, the bank or cathode electrode corresponds to the same in claim 14 of patent ‘164.
As for claim 14, the second line pad corresponds to the same in claim 1 of patent ‘164.
As for claim 15, the first gate low-potential voltage line, second gate low-potential voltage line, and third gate low-potential voltage line correspond to the same in claim 16 of patent ‘164.
As for claim 16, the bank or cathode electrode corresponds to the same in claim 1 of patent ‘164.
As for claim 17, the clock signal pad, first line pad and second line pad correspond to the same in claims 1 and 17 of patent ‘164.
As for claim 18, the additional pad corresponds to the second additional pad in claim 18 of patent ‘164.
As for claim 19, the ground pad correspond to the same in claim 19 of patent ‘164.
As for claim 20, the driving circuit corresponds to the gate driving circuit in claim 20 and the electrostatic discharge high-potential voltage line, electrostatic discharge low-potential voltage line and dummy pad correspond to the same in claims 1, 11 and 20 of patent ‘164.
Allowable Subject Matter
Claims 1-20 would be allowed with submission of terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record teaches, inter alia,
a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the driving circuit and the electrostatic discharge unit,
wherein the plurality of pads include:
an electrostatic discharge high-potential voltage pad connected with an electrostatic discharge high-potential voltage line;
an electrostatic discharge low-potential voltage pad connected with an electrostatic discharge low-potential voltage line; and
at least one dummy pad positioned between the electrostatic discharge high-potential voltage pad and the electrostatic discharge low-potential voltage pad, of claims 1 and 20. See fig. 28-30 and specifically fig. 30 regarding the configuration of the electrostatic discharge pads and dummy pad.
Lee et al. (2016/0155408), hereinafter as Lee, teaches a display device having an electrostatic discharge protection unit disposed between a display unit and a pad unit. The electrostatic discharge protection unit comprises a first signal line configured to deliver data and a control signal from a pad unit to the display unit, a second signal line, a plurality of first electrostatic discharge protection patterns which are electrically connected to the first signal line; and a plurality of second electrostatic discharge protection patterns which are electrically connected to the second signal line. Respective ones of the first electrostatic discharge protection patterns and the second electrostatic discharge protection patterns together form a plurality of electrostatic discharge protection pattern pairs, and the first and second electrostatic discharge protection patterns in each of the electrostatic discharge protection pattern pairs are separated from each other by differing distances. See fig. 1 and 10. Lee does not teach or suggest the electrostatic discharge configuration as claimed above.
Conclusion
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/TOM V SHENG/ Primary Examiner, Art Unit 2628