CTNF 19/171,517 CTNF 86358 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status. Notice of Claim Interpretation Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action. Information Disclosure Statement The information disclosure statements (IDSs) submitted on 7 April 2025 and 13 November 2025 as well as two of the IDSs submitted on 28 August 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. 06-49-09 One of the information disclosure statement filed 28 August 2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language, specifically non-patent literature document number 6. It has been placed in the application file, but the information referred to therein has not been considered. Claim Rejections - 35 USC § 112 07-30-01 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim 4 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Claim 4 includes the limitation “changing a size of the portion of the cache memory used as the L1 program cache”. The specification is silent as to any size changes of the L1 program cache. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 10-12, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Albonesi (US 6,205,537) . In regards to claim 1, Albonesi teaches a device comprising: a processor (“The processor, caches, and external interface are conventional FS structures intermixed with CAS structures such as those which have been described thus far herein.”, Col. 9, lines 10-14); a level one (L1) cache controller coupled to the processor (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63); a cache memory coupled to the L1 cache controller, wherein the L1 cache controller is capable of: using a portion of the cache memory as an L1 data cache (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63); and changing a size of the portion of the cache memory used as the L1 data cache (“As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly.”, Col. 12, lines 23-27); a level two (L2) cache controller coupled to the L1 cache controller (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63); and a tag memory coupled to the L2 cache controller (“Unlike a conventional cache in which tag arrays are physically separated from data arrays, each cache increment of the complexity-adaptive cache hierarchy of FIG. 6 is preferably a complete subcache containing both tag bits and status bits.”, Col. 12, lines 46-50); wherein the L2 cache controller is capable of: storing a set of tags associated with the L1 data cache in a portion of the tag memory (“To reconfigure without having to invalidate or transfer data, an exclusive caching policy is employed within the hierarchy, together with enforcement of a simple rule, viz.: As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly. This rule maintains a constant mapping of the index and tag bits independent of placement of the L1/L2 boundary. Two-level exclusive caching avoid a situation where two copies of the same cache block that were previously located separately in L1 and L2, are upon reconfiguration located in the same cache because of a redefinition of the L1/L2 boundary. With exclusion, a cache block is either in L1 or L2 but not both.”, Col. 12, lines 19-34); receiving an indication that the size of the portion of the cache memory used as the L1 data cache has changed (“As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly.”, Col. 12, lines 23-27); and changing a size of the portion of the tag memory associated with the set of tags based on the changing of the size of the portion of the cache memory used as the L1 data cache (“As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly.”, Col. 12, lines 23-27). In regards to claim 10, Albonesi further teaches a configuration register coupled to the L1 cache controller, wherein the L1 cache controller is capable of determining whether to resize the portion of the cache memory used as the L1 data cache based on a value stored in the configuration register (“Configuration registers (CRs) 56 which may be loaded by the hardware and by special instructions serve to set the configuration of each dynamic hardware structure and the clock speed of the chip.”, Col. 13, lines 47-51). In regards to claims 11 and 20, Albonesi teaches a device comprising: a memory (“Cache memory, or simply cache, is high speed local memory which is used to increase the execution speed of a program (i.e., the throughput) by storing a duplicate of the contents of a portion of the main memory.”, Col. 1, lines 54-58); and a cache controller coupled to the memory and associated with a first level of a cache hierarchy (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63), wherein the cache controller is capable of: allocating a portion of the memory to storing a set of tags associated with a data cache of a second level of the cache hierarchy (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63; “Unlike a conventional cache in which tag arrays are physically separated from data arrays, each cache increment of the complexity-adaptive cache hierarchy of FIG. 6 is preferably a complete subcache containing both tag bits and status bits.”, Col. 12, lines 46-50); receiving an indication that a size of the data cache has changed (“As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly.”, Col. 12, lines 23-27); and changing a size of the portion of the memory allocated to storing the set of tags in response to the indication (“As an increment is added to (or subtracted from) the L1 cache, its (i.e., the cache's) size and associativity are increased (or decreased) by the increment size and associativity, and the L2 cache size and associativity are changed accordingly.”, Col. 12, lines 23-27). In regards to claim 12, Albonesi further teaches that the cache controller is a level two cache controller and the data cache is a level one data cache (“Cache increments are assigned to L1 and L2 caches as needed for the particular application to be executed.”, Col. 11, lines 62-63) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2, 3, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Albonesi (US 6,205,537) in view of Joshi et al. (US 2012/0210066) . In regards to claims 2 and 13, Albonesi teaches claims 1 and 11. Albonesi fails to teach that the L2 cache controller is capable of completing a first set of cache requests that precede the indication prior to the changing of the size of the portion of the tag memory associated with the set of tags. Joshi teaches that the L2 cache controller is capable of completing a first set of cache requests that precede the indication prior to the changing of the size of the portion of the tag memory associated with the set of tags (“CFS 1712 waits for any outstanding I/O data traffic to and from the cache storage to complete in step 1806. In step 1807, CFS 1712 notifies the VLUN driver that I/Os are complete. Once the outstanding I/O transfers complete, a CFS stall is engaged. Thus the VLUN driver initiates the resizing from 4 GB to 8 GB in step 1808 and instructs the SCSI filter 1716 that the new allocation of cache storage space is 8 GB in step 1810. In step 1812, the SCSI filter 1716 then instructs CFS to resize the allocation of storage space to 8 GB.”, paragraph 0127). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Joshi such that the L2 cache controller is capable of completing a first set of cache requests that precede the indication prior to the changing of the size of the portion of the tag memory associated with the set of tags in order to avoid losing any data. In regards to claims 3 and 14, Joshi further teaches the L2 cache controller is capable of stalling a second set of cache requests that follow the indication (“In step 1804, the VLUN driver instructs the SCSi 1716 filter to stop sending I/O data traffic relating to the caching of data during the dynamic provisioning or re-provisioning of cache storage space. The SCSI filter 1716 instructs CFS 1712 that a resize is about to take place, so stop sending I/O data traffic to the cache storage device 1710.”, paragraph 0127) until the changing of the size of the portion of the tag memory associated with the set of tags is complete (“In step 1814, control is returned to SCSI filter 1716, and in step 1816 the SCSI filter 1716 instructs VLUN driver 1722 that the provision change of cache storage space for virtual machine 1704 is completed. In step 1818 the VLUN driver instructs SCSI filter to resume operations. In step 1820, the SCSI filter instructs CFS to resume operations.”, paragraph 0127) . 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Albonesi (US 6,205,537) in view of Semeraro et al. (“Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor”) . In regards to claim 4, Albonesi further teaches that the L1 cache controller is capable of: using a portion of the cache memory as an L1 program cache that is distinct from the L1 data cache (“In superscalar processors, both present and projected, these structures may include instruction cache hierarchy”, Col. 13, lines 22-25). Albonesi fails to teach changing a size of the portion of the cache memory used as the L1 program cache. Semeraro teaches changing a size of the portion of the cache memory used as the L1 program cache (“In the front end, the instruction cache and branch predictor are jointly resizable (i.e., each cache configuration is paired with a branch predictor sized to operate at the frequency of the cache).”, section 2, paragraph 6) which permits applications with larger instruction footprints to be accommodated (section 2, paragraph 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Semeraro to include changing a size of the portion of the cache memory used as the L1 program cache which permits applications with larger instruction footprints to be accommodated ( id .) . 07-21-aia AIA Claim s 5, 6, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Albonesi (US 6,205,537) in view of Tran et al. (US 2012/0191914) . In regards to claim 5, Albonesi further teaches that the portion of the tag memory associated with the set of tags is a first portion (“Unlike a conventional cache in which tag arrays are physically separated from data arrays, each cache increment of the complexity-adaptive cache hierarchy of FIG. 6 is preferably a complete subcache containing both tag bits and status bits.”, Col. 12, lines 46-50). Albonesi fails to teach that the L2 cache controller is capable of: storing a set of coherence data associated with the L1 data cache in a second portion of the tag memory; and changing a size of the second portion of the tag memory associated with the set of coherence data based on the changing of the size of the portion of the cache memory used as the L1 data cache. Tran teaches that the L2 cache controller is capable of: storing a set of coherence data associated with the L1 data cache in a second portion of the tag memory (“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache.”, paragraph 0050); and changing a size of the second portion of the tag memory associated with the set of coherence data based on the changing of the size of the portion of the cache memory used as the L1 data cache (“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050) in order “to implement snoop read and write coherence” (paragraph 0050). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Tran such that the L2 cache controller is capable of: storing a set of coherence data associated with the L1 data cache in a second portion of the tag memory; and changing a size of the second portion of the tag memory associated with the set of coherence data based on the changing of the size of the portion of the cache memory used as the L1 data cache in order “to implement snoop read and write coherence” ( id .). In regards to claim 6, Albonesi teaches claim 1. Albonesi fails to teach that the L2 cache controller includes: a first interface coupled to the L1 cache controller and capable of receiving cache requests and providing responses to the cache requests to the L1 cache controller; and a sideband interface coupled to the L1 cache controller that is distinct from the first interface and that is capable of receiving the indication that the size of the portion of the cache memory used as the L1 data cache has changed. Tran teaches that the L2 cache controller includes: a first interface coupled to the L1 cache controller and capable of receiving cache requests and providing responses to the cache requests to the L1 cache controller (“These level one caches are bidirectionally connected to L2 130.”, paragraph 0048); and a sideband interface coupled to the L1 cache controller that is distinct from the first interface and that is capable of receiving the indication that the size of the portion of the cache memory used as the L1 data cache has changed (“As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730.”, paragraph 0049; “Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050) in order “to implement snoop read and write coherence” (paragraph 0050). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Tran such that the L2 cache controller includes: a first interface coupled to the L1 cache controller and capable of receiving cache requests and providing responses to the cache requests to the L1 cache controller; and a sideband interface coupled to the L1 cache controller that is distinct from the first interface and that is capable of receiving the indication that the size of the portion of the cache memory used as the L1 data cache has changed in order “to implement snoop read and write coherence” ( id .). In regards to claim 15, Albonesi further teaches the portion of the memory allocated to storing the set of tags is a first portion (“Unlike a conventional cache in which tag arrays are physically separated from data arrays, each cache increment of the complexity-adaptive cache hierarchy of FIG. 6 is preferably a complete subcache containing both tag bits and status bits.”, Col. 12, lines 46-50). Albonesi fails to teach that the cache controller is capable of: allocating a second portion of the memory to storing a set of coherence data associated with the data cache; and changing a size of the second portion of the memory allocated to storing the set of coherence data in response to the indication. Trans teaches that the cache controller is capable of: allocating a second portion of the memory to storing a set of coherence data associated with the data cache (“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache.”, paragraph 0050); and changing a size of the second portion of the memory allocated to storing the set of coherence data in response to the indication (“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050) in order “to implement snoop read and write coherence” (paragraph 0050). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Trans such that the cache controller is capable of: allocating a second portion of the memory to storing a set of coherence data associated with the data cache; and changing a size of the second portion of the memory allocated to storing the set of coherence data in response to the indication in order “to implement snoop read and write coherence” ( id .). In regards to claim 16, Albonesi teaches claim 11. Albonesi fails to teach that the cache controller includes: a first interface capable of receiving cache requests from the second level of the cache hierarchy and providing responses to the cache requests to the second level of the cache hierarchy; and a sideband interface that is distinct from the first interface and that is capable of receiving the indication that that the size of the data cache has changed. Tran teaches that the cache controller includes: a first interface capable of receiving cache requests from the second level of the cache hierarchy and providing responses to the cache requests to the second level of the cache hierarchy (“These level one caches are bidirectionally connected to L2 130.”, paragraph 0048); and a sideband interface that is distinct from the first interface and that is capable of receiving the indication that that the size of the data cache has changed (“As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730.”, paragraph 0049; “Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050) in order “to implement snoop read and write coherence” (paragraph 0050). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Albonesi with Tran such that the cache controller includes: a first interface capable of receiving cache requests from the second level of the cache hierarchy and providing responses to the cache requests to the second level of the cache hierarchy; and a sideband interface that is distinct from the first interface and that is capable of receiving the indication that that the size of the data cache has changed in order “to implement snoop read and write coherence” ( id .) . Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-3, 5, 6, 10-16, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 8, 8, 13, 8, 8, 14, 8, 8, 8, 13, 8, 8, and 1 of U.S. Patent No. 12,271,314 in view of Tran et al. (US 2012/0191914) . In regards to claim 1, claim 8 of U.S. Patent No. 12,271,314 teaches a device comprising (“A device comprising”): a processor (“a processor”); a first cache controller coupled to the processor (“a first cache controller coupled to the processor”); a cache memory coupled to the first cache controller (“a cache memory coupled to the first cache controller”), wherein the first cache controller is capable of: using a portion of the cache memory as a cache (“utilize a portion of the cache memory as a cache”); and changing a size of the portion of the cache memory used as the cache (“ a signal that specifies that a cache size operation has been completed”); a second cache controller coupled to the first cache controller (“a second cache controller coupled to the first cache controller”); and a tag memory coupled to the second cache controller (“a tag memory coupled to the second cache controller”); wherein the second cache controller is capable of (“wherein the second cache controller is configured to”): storing a set of tags associated with the cache in a portion of the tag memory (“utilize a portion of the tag memory as a shadow cache associated with the cache”); receiving an indication that the size of the portion of the cache memory used as the cache has changed (“receive, from the first cache controller, a signal that specifies that a cache size operation has been completed”); and changing a size of the portion of the tag memory associated with the set of tags (“resize the shadow cache”) based on the changing of the size of the portion of the cache memory used as the cache (“based on the signal specifying that the cache size operation has been completed”). Claim 8 of U.S. Patent No. 12,271,314 fails to teach that the first cache controller is a L1 cache controller; wherein the cache is an L1 data cache; wherein the second cache controller is a L2 cache controller. Tran teaches that the first cache controller is a L1 cache controller (data memory controller (DMC) 710, figure 7); wherein the cache is an L1 data cache (L1D cache 123, figure 7); wherein the second cache controller is a L2 cache controller (unified memory controller (UMC) 730, figure 7) which “improves performance and minimizes dynamic power” (abstract). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 8 of U.S. Patent No. 12,271,314 with Tran such that the first cache controller is a L1 cache controller; wherein the cache is an L1 data cache; wherein the second cache controller is a L2 cache controller which “improves performance and minimizes dynamic power” ( id .). In regards to claim 2, claim 8 of U.S. Patent No. 12,271,314 further teaches that the L2 cache controller is capable of completing a first set of cache requests that precede the indication prior to the changing of the size of the portion of the tag memory associated with the set of tags (“complete a set of cache transactions; and based on completion of the set of cache transactions, resize the shadow cache”). In regards to claim 3, claim 13 of U.S. Patent No. 12,271,314 further teaches that the L2 cache controller is capable of stalling a second set of cache requests that follow the indication until the changing of the size of the portion of the tag memory associated with the set of tags is complete (“during the completing of the set of cache transactions: receive a transaction; and stall the transaction until after the resizing of the shadow cache”). In regards to claim 5, Tran further teaches that the portion of the tag memory associated with the set of tags is a first portion (L2 tags 731, figure 7); and the L2 cache controller is capable of: storing a set of coherence data associated with the L1 data cache in a second portion of the tag memory (“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache.”, paragraph 0050); and changing a size of the second portion of the tag memory associated with the set of coherence data based on the changing of the size of the portion of the cache memory used as the L1 data cache (“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050). In regards to claim 6, Tran further teaches that the L2 cache controller includes: a first interface coupled to the L1 cache controller and capable of receiving cache requests and providing responses to the cache requests to the L1 cache controller (“These level one caches are bidirectionally connected to L2 130.”, paragraph 0048); and a sideband interface coupled to the L1 cache controller that is distinct from the first interface and that is capable of receiving the indication that the size of the portion of the cache memory used as the L1 data cache has changed (“As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730.”, paragraph 0049; “Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050). In regards to claim 10, claim 14 of U.S. Patent No. 12,271,314 further teaches a configuration register coupled to the L1 cache controller (“the first cache controller is coupled to the configuration register”), wherein the L1 cache controller is capable of determining whether to resize the portion of the cache memory used as the L1 data cache based on a value stored in the configuration register (“the first cache controller is configured to, based on the value stored in the configuration register: determine to resize the cache”). In regards to claim 11, claim 8 of U.S. Patent No. 12,271,314 teaches a device comprising (“A device comprising”): a memory (“a tag memory”); and a cache controller (“a second cache controller “) coupled to the memory (“a tag memory coupled to the second cache controller”), wherein the cache controller is capable of (“wherein the second cache controller is configured to”): allocating a portion of the memory to storing a set of tags associated with a data cache (“utilize a portion of the tag memory as a shadow cache associated with the cache”); receiving an indication that a size of the data cache has changed (“based on the signal specifying that the cache size operation has been completed”); and changing a size of the portion of the memory allocated to storing the set of tags in response to the indication (“resize the shadow cache”). Claim 8 of U.S. Patent No. 12,271,314 fails to teach the cache controller is associated with a first level of a cache hierarchy; wherein the data cache is of a second level of the cache hierarchy. Tran teaches the cache controller is associated with a first level of a cache hierarchy (“As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730.”, paragraph 0049); wherein the data cache is of a second level of the cache hierarchy (L2 130, figure 7) which “improves performance and minimizes dynamic power” (abstract). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 8 of U.S. Patent No. 12,271,314 with Tran such that the cache controller is associated with a first level of a cache hierarchy; wherein the data cache is of a second level of the cache hierarchy which “improves performance and minimizes dynamic power” ( id .). In regards to claim 12, Tran further teaches that the cache controller is a level two cache controller (UMC 730, figure 7) and the data cache is a level one data cache (L1d 123, figure 7). In regards to claim 13, claim 8 of U.S. Patent No. 12,271,314 further teaches that the cache controller is capable of completing a first set of cache requests that precede the indication prior to the changing of the size of the portion of the memory allocated to storing the set of tags (“complete a set of cache transactions; and based on completion of the set of cache transactions, resize the shadow cache”). In regards to claim 14, claim 13 of U.S. Patent No. 12,271,314 further teaches that the cache controller is capable of stalling a second set of cache requests that follow the indication until the changing of the size of the portion of the memory allocated to storing the set of tags is complete (“during the completing of the set of cache transactions: receive a transaction; and stall the transaction until after the resizing of the shadow cache”). In regards to claim 15, Tran further teaches that the portion of the memory allocated to storing the set of tags is a first portion (L2 tags 731, figure 7); and the cache controller is capable of: allocating a second portion of the memory to storing a set of coherence data associated with the data cache (“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache.”, paragraph 0050); and changing a size of the second portion of the memory allocated to storing the set of coherence data in response to the indication (“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050). In regards to claim 16, Tran further teaches that the cache controller includes: a first interface capable of receiving cache requests from the second level of the cache hierarchy and providing responses to the cache requests to the second level of the cache hierarchy (“These level one caches are bidirectionally connected to L2 130.”, paragraph 0048); and a sideband interface that is distinct from the first interface and that is capable of receiving the indication that that the size of the data cache has changed (“As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730.”, paragraph 0049; “Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM.”, paragraph 0050). In regards to claim 20, claim 1 of U.S. Patent No. 12,271,314 teaches a method comprising (“A method comprising”): allocating, by a cache controller, a portion of a memory to storing a set of tags associated with a cache (“utilizing, by a cache controller, a tag memory as a shadow cache of a cache”); receiving, by the cache controller, an indication that a size of the data cache has changed (“receiving, by the cache controller, a signal that indicates that a cache size operation has been completed on the cache”); and changing a size of the portion of the memory allocated to storing the set of tags (“resizing, by the cache controller, the shadow cache”) in response to the indication (“based on the signal indicating that the cache size operation has been completed”). Claim 1 of U.S. Patent No. 12,271,314 fails to teach that the cache controller is associated with a first level of a cache hierarchy; wherein the cache is a data cache of a second level of the cache hierarchy. Tran teaches that the cache controller is associated with a first level of a cache hierarchy (data memory controller (DMC) 710, figure 7); wherein the cache is a data cache of a second level of the cache hierarchy (L2 cache 130, figure 7) which “improves performance and minimizes dynamic power” (abstract). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 1 of U.S. Patent No. 12,271,314 with Tran such that the cache controller is associated with a first level of a cache hierarchy; wherein the cache is a data cache of a second level of the cache hierarchy which “improves performance and minimizes dynamic power” ( id .) . 08-36 AIA Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,271,314 in view of Tran et al. (US 2012/0191914) and Semeraro et al. (“Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor”) . In regards to claim 4, Tran further teaches the L1 cache controller is capable of: using a portion of the cache memory as an L1 program cache that is distinct from the L1 data cache (Level one instruction cache (L1I) 121 vs level one data cache (L1D) 123, figure 7). Claim 8 of U.S. Patent No. 12,271,314 in view of Tran fails to teach that the L1 cache controller is capable of: changing a size of the portion of the cache memory used as the L1 program cache. Semeraro teaches that the L1 cache controller is capable of: changing a size of the portion of the cache memory used as the L1 program cache (“In the front end, the instruction cache and branch predictor are jointly resizable (i.e., each cache configuration is paired with a branch predictor sized to operate at the frequency of the cache).”, section 2, paragraph 6) which permits applications with larger instruction footprints to be accommodated (section 2, paragraph 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 8 of U.S. Patent No. 12,271,314 with Tran and Semeraro such that the L1 cache controller is capable of: changing a size of the portion of the cache memory used as the L1 program cache which permits applications with larger instruction footprints to be accommodated ( id .) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7-9 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach “a second signal that specifies whether the cache operation includes the changing of the size of the data cache” in conjunction with the other claim limitations, nor would it have been obvious . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nathan Sadler/Primary Examiner, Art Unit 2139 1 June 2026 Application/Control Number: 19/171,517 Page 2 Art Unit: 2139 Application/Control Number: 19/171,517 Page 3 Art Unit: 2139 Application/Control Number: 19/171,517 Page 5 Art Unit: 2139 Application/Control Number: 19/171,517 Page 6 Art Unit: 2139 Application/Control Number: 19/171,517 Page 7 Art Unit: 2139 Application/Control Number: 19/171,517 Page 8 Art Unit: 2139 Application/Control Number: 19/171,517 Page 9 Art Unit: 2139 Application/Control Number: 19/171,517 Page 10 Art Unit: 2139 Application/Control Number: 19/171,517 Page 11 Art Unit: 2139 Application/Control Number: 19/171,517 Page 12 Art Unit: 2139 Application/Control Number: 19/171,517 Page 13 Art Unit: 2139 Application/Control Number: 19/171,517 Page 14 Art Unit: 2139 Application/Control Number: 19/171,517 Page 15 Art Unit: 2139 Application/Control Number: 19/171,517 Page 16 Art Unit: 2139 Application/Control Number: 19/171,517 Page 17 Art Unit: 2139 Application/Control Number: 19/171,517 Page 18 Art Unit: 2139 Application/Control Number: 19/171,517 Page 19 Art Unit: 2139 Application/Control Number: 19/171,517 Page 20 Art Unit: 2139 Application/Control Number: 19/171,517 Page 21 Art Unit: 2139 Application/Control Number: 19/171,517 Page 22 Art Unit: 2139 Application/Control Number: 19/171,517 Page 23 Art Unit: 2139 Application/Control Number: 19/171,517 Page 24 Art Unit: 2139 Application/Control Number: 19/171,517 Page 25 Art Unit: 2139 Application/Control Number: 19/171,517 Page 26 Art Unit: 2139 Application/Control Number: 19/171,517 Page 27 Art Unit: 2139
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