DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are pending in this application.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/019579, filed on 02/09/2016.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/07/2025 and 01/16/2026 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities: Claim 7 recites the limitation “a pair of the pn diodes” in line 2 of the claim. This appears to mean “a pair of pn diodes”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. Japanese Patent Document JP 2011-193016 A (hereinafter “Kono”) and further in view of Nakamura et al. U.S. Patent Application 2011/0215400 (hereinafter “Nakamura”).
Regarding claim 1, Kono teaches a semiconductor device (refer to title and abstract), comprising: a semiconductor chip (refer to [0023]) which is a semiconductor substrate (refer to fig.1) having a first surface (i.e. first surface in the figure below)(fig.1) and a second surface (i.e. second surface in the figure below)(fig.1) and formed in a tetragonal shape in a plan view (refer to fig.3); a switching element (refer to IGBT area in the figure below)(fig.1)(refer also to fig.6) that is formed on the semiconductor substrate (refer to IGBT area and the figure below)(fig.1) and performs a switching operation between a first electrode (i.e. emitter electrode 111)(figs.1 and 6) provided on the first surface side of the semiconductor substrate (refer to emitter electrode 111)(fig.6) and a second electrode (i.e. collector electrode 100)(figs.1 and 6) provided on the second surface side of the semiconductor substrate (Refer to collector electrode 100)(fig.1), in response to a signal input to a control electrode (i.e. gate electrode 108)(fig.1)(refer also to gate pad 204)(fig.3) provided on the first surface side of the semiconductor substrate (refer to gate electrode 108)(fig.1); a gate finger (i.e. gate wiring 201)(fig.3) that extends from the control electrode along an outer periphery of the semiconductor chip (refer to fig. 3 and [0023]) and further extends across a central portion of the semiconductor chip (refer to fig.3); a temperature sense element (refer to [0023]: “temperature detection element”), capable of outputting a signal dependent on temperature (implicit); and a third electrode (i.e. temperature detection pad 202)(fig.3) and a fourth electrode (i.e. temperature detection pad 203)(fig.3) that are electrically connected to the temperature sense element (refer to [0023]), wherein the control electrode, the third electrode and the fourth electrode have substantially the same size and the same shape as one another (implicit)(refer to fig.3), the control electrode is arranged at a center portion of one side of the semiconductor chip (implicit)(refer to fig.3), and the third and fourth electrodes are arranged side by side on one side of the control electrode (implicit)(refer to fig.3) along the one side where the control electrode is arranged (implicit)(refer to fig.3), the temperature sense element is arranged adjacent to the gate finger (implicit)(refer to fig.3); however, Kono does not teach the temperature sense element provided on the first surface side. However, Nakamura teaches the temperature sense element provided on the first surface side (refer to Nakamura diodes DD1)(fig.12). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono to include the temperature sense element placement of Nakamura to provide the advantage of accurately detecting the temperature of the switching device (refer to Nakamura [0106]).
Regarding claim 2, Kono and Nakamura teach the semiconductor device according to claim 1, comprising a diode element (refer to Nakamura diodes DD1)(figs.11 and 12) capable of outputting a temperature-dependent signal as the temperature sense element (refer to Nakamura [0106] and [0107]).
Regarding claim 3, Kono and Nakamura teach the semiconductor device according to claim 2, wherein the anode and cathode of the diode element are connected to the third electrode and the fourth electrode, respectively (implicit)(refer to Nakamura figure 11).
Regarding claim 4, Kono and Nakamura teach the semiconductor device according to claim 1; wherein the switching element includes a MISFET (refer to Kono [0014]: MOSFET is a type of MISFET)(refer also to Nakamura figures 14 and 15) in which the first electrode includes a source electrode (refer to Kono [0014])(i.e. Nakamura source wiring 10S and pad electrode PDS1)(fig.14), the second electrode includes a drain electrode (refer to Kono [0014])(i.e. Nakamura back electrode BE)(fig.14)(refer also to Nakamura [0135]), and the control electrode includes a gate electrode (refer to Kono [0014])(i.e. Nakamura gate wiring 10G and pad electrode PDG1)(fig.14), the source electrode has regions (refer to Kono IGBT regions 206)(fig.3)(refer also to Kono [0014]) that are divided into two by the gate finger crossing the central portion of the semiconductor chip (refer to Kono gate wiring 201)(fig.3), the third electrode and the fourth electrode are arranged adjacent to a periphery of one of the regions of the divided source electrode (refer to Kono fig.3).
Regarding claim 5, Kono and Nakamura teach the semiconductor device according to claim 1, wherein the switching element includes a MISFET (refer to Kono [0014])(refer also to Nakamura figures 14 and 15) in which the first electrode includes a source electrode (refer to Kono [0014])(i.e. Nakamura source wiring 10S and pad electrode PDS1)(fig.14), the second electrode includes a drain electrode (refer to Kono [0014])(i.e. Nakamura gate wiring 10G and pad electrode PDG1)(fig.14), and the control electrode includes a gate electrode (refer to Kono [0014])(i.e. Nakamura gate wiring 10G and pad electrode PDG1)(fig.14).
Regarding claim 6, Kono and Nakamura teach the semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are connected to terminals that are electrically independent from terminals to which the first electrode and the second electrode of the switching element are respectively connected (refer to Nakamura fig.11).
Regarding claim 7, Kono and Nakamura teach the semiconductor device according to claim 1, wherein the temperature sense element includes a serial connection unit in which at least a pair of the pn diodes are connected in series or in series in a reverse direction to each other (refer to Nakamura DD1)(fig.11).
Regarding claim 15, Kono and Nakamura teach the semiconductor device according to claim 1, wherein the switching element includes a trench-gate MISFET (Refer to Nakamura figs. 14 and 15), the trench-gate MISFET comprising: a gate trench (refer to Nakamura [0134]) formed in the semiconductor chip (implicit) and defining unit cells (refer to Nakamura [0134]) ,a gate electrode (i.e. Nakamura gate electrode 7)(figs.14 and 15) embedded in the gate trench (implicit), a first conductivity type body region formed on a surface portion of the unit cells (refer to Nakamura [0136] and [0137]), a second conductivity type source region formed on a surface portion of the body region (refer to Nakamura [0136] and [0137]), and a second conductivity type drain region formed on the opposite side of the source region with respect to the body region (refer to Nakamura [0136] and [0137]).
Regarding claim 16, Kono and Nakamura teach the semiconductor device according to claim 1, however, they do not teach wherein the temperature sense element is arranged in a temperature sense region between the third electrode and the fourth electrode. However, Kono teaches a sense element (i.e. sense resistor 600)(fig.6)(refer also to [0030]) arranged in a sense region (i.e. IGBT sense region 206)(fig.3)(refer also to [0030]) between two electrodes (i.e. electrodes 205 and 207)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono and Nakamura to arrange the temperature sense element in a temperature sense region between the third electrode and the fourth electrode similar to the sense resistor arranged in the sense region between the two electrodes of Kono to provide the advantage of simplifying the connection of the temperature sense element to the electrodes.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kono and Nakamura as applied to claim 1 above, and further in view of Asai Japanese Patent Document JP 2008-172132 A (hereinafter “Asai”).
Regarding claim 8, Kono and Nakamura teach the semiconductor device according to claim 1; however, they do not teach wherein the temperature sense element includes at least a pair of pn diodes are connected in parallel in a reverse direction to each other. However, Asai teaches wherein the temperature sense element includes at least a pair of pn diodes (i.e. diodes 21 and 22)(fig.2) are connected in parallel in a reverse direction to each other (implicit)(refer to fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono and Nakamura to include the parallel diodes of Asai to provide the advantage of averaging the temperature sense by each diode in order to more accurately measure the temperature.
Regarding claim 9, Kono and Nakamura teach the semiconductor device according to claim 1, wherein the temperature sense element includes a serial connection unit (refer to Nakamura diode DD1)(fig.11) in which at least a pair of pn diodes are connected in series (refer to Nakamura diode DD1)(fig.11); however, they do not teach the serial connection units are connected in parallel in a reverse direction to each other. However, Asai teaches wherein the serial connection units are connected in parallel in a reverse direction to each other (refer to diodes 21 and 22)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono and Nakamura to include the parallel units of Asai to provide the advantage of averaging the temperature sense by each serial connection unit in order to more accurately measure the temperature.
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kono and Nakamura as applied to claim 1 above, and further in view of Stecher.
Regarding claim 10, Kono and Nakamura teach the semiconductor device according to claim 1; however, they do not teach wherein the semiconductor substrate includes an SiC semiconductor layer. However, Stecher teaches wherein the semiconductor substrate includes an SiC semiconductor layer (refer to [0021]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono and Nakamura to include the SiC semiconductor layer of Stecher to provide the advantage of using a substrate that is commonly employed in semiconductor technology.
Regarding claim 11, Kono, Nakamura, and Stecher teach the semiconductor device according to claim 10, wherein the temperature sense element is formed in a polysilicon layer on the SiC semiconductor layer (refer to Kono [0023])(refer also to Nakamura [0140]).
Regarding claim 12, Kono, Nakamura, and Stecher teach the semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sense element has the same thickness as a gate electrode of the switching element (refer to Nakamura [0137]).
Regarding claim 13, Kono, Nakamura, and Stecher teach the semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sense element includes a selectively introduced first conductivity type impurity region and a second conductivity type impurity region (refer to Nakamura [0140]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kono and Nakamura as applied to claim 1 above, and further in view of Sakamoto U.S. Patent No. 6,323,518 (hereinafter “Sakamoto”).
Regarding claim 17, Kono and Nakamura teach the semiconductor device according to claim 1; however, they do not teach wherein the temperature sense element includes a first conductivity type region formed in the semiconductor substrate and a second conductivity type region surrounding the first conductivity type region. However, Sakamoto teaches wherein the temperature sense element includes a first conductivity type region formed in the semiconductor substrate (refer to [0140]) and a second conductivity type region surrounding the first conductivity type region (refer to [0140]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kono and Nakamura to include the conductivity regions of Sakamoto to provide the advantage of having no characteristic degradation of the blocking voltage (refer to Sakamoto col. 7 lines 28-45).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5, 7, 10, and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 7, 10, 13, and 14 of U.S. Patent No. 12,300,694 (hereinafter “’694”). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 9, and 14 of ‘694 contain all of the limitations of claim 1 of the instant application; claims 5, 14, 7, 10, and 13 of ‘694 contain all of the limitations of claims 2, 3, 5, 7, 10, and 16 of the instant application, respectively.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 14 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 14, especially wherein the polysilicon layer forming the temperature sense element includes a base layer of a second conductivity type and an impurity region of a first conductivity type selectively formed on a surface of the base layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838
Prosecution Insights