DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a1)/(a2) as being anticipated by SANDISK (WO2020/031475).
Regarding claim 1, SANDISK discloses a memory device [FIG. 1], comprising: an array of memory cells [FIG. 4, 8A: BLK0-BLK3 of memory cells]; word lines respectively coupled to rows of the memory cells [FIG. 3: WL lines coupled to Row decoder and BLK_0 to BLK_7]; and a peripheral circuit coupled to the array of memory cells through the word lines [FIG. 3: Row decoder] and configured to: apply a read voltage to a select word line of the word lines [FIG. 12B: apply voltage of VWLn to selected word line]; and discharge the select word line from a voltage greater than the read voltage to a first recovery voltage that is greater than a supply voltage, wherein the discharging of the select word line stops when a voltage of the select word line reaches the first recovery voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 2, SANDISK discloses the memory device of claim 1, wherein the peripheral circuit is further configured to: apply a pass voltage to an unselect word line of the word lines [FIG. 12E: ramp down of VWL_ds from program pass voltage of VWL_ds to recovery voltage of Vrec]; and discharge the unselect word line from the pass voltage to a second recovery voltage that is greater than the supply voltage [FIG. 12E: ramp down of VWL_ds from program pass voltage of VWL_ds to recovery voltage of Vrec].
Regarding claim 3, SANDISK discloses the memory device of claim 2, wherein the first recovery voltage is smaller than the second recovery voltage [FIG. 12G: maintain VWLn at Vcc which is equal to recovery voltage of 3V lower than 4.5V].
Regarding claim 4, SANDISK discloses the memory device of claim 2, wherein the unselect word line is immediately adjacent to the select word line [FIG. 8C, 8A; ¶0133].
Regarding claim 5, SANDISK discloses the memory device of claim 4, wherein the peripheral circuit is configured to start discharging the select word line and the unselect word line at a same time [¶0058].
Regarding claim 6, SANDISK discloses the memory device of claim 1, wherein the peripheral circuit comprises a word line driver configured to: apply the read voltage to the select word line and control logic coupled to the word line driver [FIG. 12B, ¶00175: apply VWLn to selected word line]; and set a duration for the word line driver to discharge the select word line [¶00175: the ramp down being temporary].
Regarding claim 7, SANDISK discloses the memory device of claim 1, wherein the peripheral circuit comprises a word line driver configured to: apply the read voltage to the select word line and control logic coupled to the word line driver [FIG. 12B, ¶00175: apply VWLn to selected word line]; and set the first recovery voltage for the word line driver to discharge the select word line [FIG. 12D: ramp down VWL_ss to recovery voltage Vrec].
Regarding claim 8, SANDISK discloses the memory device of claim 1, wherein a select row of the rows of memory cells coupled to the select word line is configured to store two or more pages of data [FIG. 8B]; and the peripheral circuit is further configured to perform two or more read operations in sequence to read at different levels [¶00104].
Regarding claim 9, SANDISK discloses the memory device of claim 8, wherein the peripheral circuit is further configured to discharge the select word line from a voltage greater than a last read voltage to a respective recovery voltage that is greater than the supply voltage in each read operation of the two or more read operations [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 10, SANDISK discloses the memory device of claim 9, wherein the peripheral circuit is further configured to apply the voltage greater than the last read voltage before discharging the select word line in each read operation of the two or more read operations [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 11, SANDISK discloses the memory device of claim 1, wherein the peripheral circuit is further configured to apply a pre-pulse voltage to the select word line before applying the read voltage [¶0054, 0198].
Regarding claim 12, SANDISK discloses the memory device of claim 1, wherein the supply voltage comprises a Vdd voltage [FIG. 8D, 13A-13H].
Regarding claim 13, SANDISK discloses a method for reading a memory device comprising memory cells, comprising, in a first read operation on a select row of the memory cells coupled to a select word line: applying [[a]] two or more different first read voltages in sequence to the select word line [FIG. 12B: apply voltage of VWLn to selected word line]; applying a voltage greater than a last first read voltage of the two or more different first read voltages [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss]; and discharging the select word line from the voltage greater than the last first read voltage to a first recovery voltage that is greater than a supply voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 14, SANDISK discloses the method of claim 13, further comprising: applying a pass voltage to an unselect word line coupled to an unselect row of the memory cells [FIG. 12B: apply voltage of VWLn to selected word line]; and discharging the unselect word line from the pass voltage to a second recovery voltage that is greater than the supply voltage, wherein the second recovery voltage is different from the first recovery voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 15, SANDISK discloses the method of claim 13, in a second read operation following the first read operation on the select row of the memory cells, further comprising: applying two or more different second read voltages in sequence to the select word line [¶00104]; applying a voltage greater than a last second read voltage of the two or more different second read voltages [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss]; and discharging the select word line from the voltage greater than the last second read voltage to a second recovery voltage that is greater than the supply voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 16, SANDISK discloses the method of claim 13, further comprising: applying a pre-pulse voltage to the select word line before applying the two or more different first read voltages in the first read operation [¶0054, 0198].
Regarding claim 17, SANDISK discloses the method of claim 13, further comprising setting a duration to discharge the select word line [¶00175: the ramp down being temporary].
Regarding claim 18, SANDISK discloses the method of claim 13, further comprising setting the first recovery voltage to discharge the select word line [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 19, SANDISK discloses the method of claim 13, wherein the discharging of the select word line stops when a voltage of the select word line reaches the first recovery voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss].
Regarding claim 20, SANDISK discloses t system, comprising: a memory device configured to store data [FIG. 4, 8A: BLK0-BLK3 of memory cells], the memory device comprising: an array of memory cells; word lines respectively coupled to rows of the memory cells [FIG. 4, 8A: BLK0-BLK3 of memory cells]; and a peripheral circuit coupled to the array of memory cells through the word lines and configured to, in a read operation on a select row of the rows of memory cells coupled to a select word line of the word lines: apply a read voltage to a select word line of the word lines [FIG. 12B: apply voltage of VWLn to selected word line]; and discharge the select word line from a voltage greater than the read voltage to a recovery voltage that is greater than a supply voltage, wherein the discharging of the select word line stops when a voltage of the select word line reaches the recovery voltage [FIG. 12D-12H: ramp down VWL_ds from program pass voltage of VWL ds to recovery voltage of Vrec, ramp down VWL_ss from program pass voltage of VWL_ss to recovery voltage of Vres_ss]; and a memory controller coupled to the memory device and configured to control the memory device [FIG. 2-3].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lu et al. (US10,762,973) discloses suppressing program disturb during program recovery in memory device wherein program disturb is suppressed during a program recovery phase.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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