The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 7-14, and 17-20 of patent application 12271244. The table listed below shows the similarity between the two and highlight the differences.
Instant Application 19171875
Patent 12271244
A method for integrated circuit power management, the method comprising:
responsive to an entry condition of a mode of a power management state,
entering the mode; and
powering on a device that is otherwise powered off in the power management state
responsive to entering the mode, wherein the device is powered on in the mode via a power
domain;
wherein the entry condition of the mode comprises an amount of data stored in a buffer
meeting a threshold.
(Currently Amended) A method for integrated circuit power management, the method comprising:
responsive to an entry condition of a mode of a power management state,
entering the mode; and
powering on a device that is otherwise powered off in the power management state responsive to entering the mode,
wherein the device is powered on in the mode via a power rail that is specific to the mode;
wherein the entry condition of the mode comprises an amount of data stored for display in a display buffer falling below a threshold amount.
2. The method of claim 1, wherein the device comprises a communications path between a second device and a third device.
3. The method of claim 1, wherein the device is in a power domain that is powered off in the power management state.
4. The method of claim 1, wherein the device comprises a communications path between the buffer and a memory.
5. The method of claim 1, wherein the device comprises at least a portion of a data fabric.
6. The method of claim 1, wherein an exit condition of the mode comprises the buffer being full.
7. The method of claim 1, further comprising: in the mode, communicating, by the device, with a second device that is in a power domain that is on in the power management state.
2. (Original) The method of claim 1, wherein the device comprises a communications path between a second device and a third device.
3. (Original) The method of claim 1, wherein the device is in a power domain that is powered off in the power management state.
7. (Previously Presented) The method of claim 1, wherein the device comprises a communications path between the display buffer and a memory.
8. (Original) The method of claim 1, wherein the device comprises at least a portion of a data fabric.
9. (Previously Presented) The method of claim 1, wherein an exit condition of the mode comprises the display buffer being full.
10. (Original) The method of claim 1, further comprising: in the mode, communicating, by the device, with a second device that is in a power domain that is on in the power management state.
As shown from the table above, claims 1-3 and 7-10 of patent 12271244 teach the same concept of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Branover (US Patent Application 20190147926).
As per claim 1, Branover teaches a method [600, fig. 6] for integrated circuit [300, fig. 3] power management, the method comprising:
responsive to an entry condition of a mode of a power management state [0015, 0026, decision to enter to stutter mode which is viewed as a reduced power state. For example, the decision can be based on detection of lack activity of the client or the idleness of the client. As pointed out, Stutter mode refers to a mode when a region of the fabric is put into a reduced-power state (e.g., power-gated mode) and then the region is periodically woken up from the reduced power state to service clients].
entering the mode [0026, fig. 7 as pointed out if no activity, the client can be put in reduced power state based on the detection. For example, the decision to enter stutter mode is made based on detecting a lack of activity (i.e., idleness) of clients sharing fabric 115].
and powering on a device that is otherwise powered off in the power management state responsive to entering the mode [0026,0051, fig. 7 as pointed out form the listed paragraph during the reduced power state, while the system can power down the PLL but can also provide bypass clock to the memory during stutter mode. For example, while in stutter mode, the system can power down a PLL which provides a clock to the memory PHY (block 710). Also, the system can supply the memory PHY with a bypass clock during the stutter mode (block 715). After block 715, method 700 ends].
wherein the device is powered on in the mode via a power domain [0019, 0032-0032, as pointed out and shown in figures 1-2, the fabric is partitioning into multiple power domains, where each component is operating on specific power domain. For example, each region 202A-C of fabric 200 includes one or more components that are included within the respective region and this power-gating domain is power-gated as a group, such that every component in a dashed block labeled as region 202A is power-gated together and is brought out of power-gating mode together].
wherein the entry condition of the mode comprises an amount of data stored in a buffer meeting a threshold amount [0026, as pointed when the display buffer is full enough or fall below specific threshold, then the client can enter to the reduce power state or stutter mode. For example, in one embodiment, when the occupancy of buffer of display controller 135 is above a first threshold, system 100 can enter stutter idle state. Once the buffer occupancy falls below a second threshold, system 100 exits stutter idle mode and transitions into stutter active mode. In another embodiment, when the display panel buffer is full, which can happen during panel self-refresh mode, system 100 can enter stutter idle state].
As per claim 2, Branover teaches the device comprises a communications path between a second device and a third device [0024, as pointed out path from the display to the controller: powering up the memory controller, turning on fabric 115 power for those components on the path from display controller 135 to memory 130].
As per claim 3, Branover teaches the device is in a power domain that is powered off in the power management state [0025, 0032, multiple power domain where some of them can be power on and power off or function in different power mode].
As per claim 4, Branover teaches the device comprises a communications path between the buffer and a memory [0025, 0032, power gating domain where devices in the region can be powered off].
As per claim 5, Branover teaches the device comprises at least a portion of a data fabric [0031, figures 1-2, the device includes multiple regions of the data fabric].
As per claim 6, Branover teaches an exit condition of the mode comprises the buffer being full [0026, pontification indicated when the buffer is full or idle activity and exit].
As per claim 7, Branover teaches in the mode, communicating, by the device, with a second device that is in a power domain that is on in the power management state 0024, 0044 as pointed out path from the display to the controller: powering up the memory controller, turning on fabric 115 power for those components on the path from display controller 135 to memory 130].
As per claims 8-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 8-20 are also anticipated by Branover for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sung (US 20220029624) teaches integrated circuit and signal transmission method thereof.
Kumar (US 20170235352) teaches methods and systems for memory initialization of an integrated circuit.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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