The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claims 1-7 and 16-20 are allowed because none of the prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the foregoing limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8 and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui (US Patent Application 20150160718).
As per claim 8, Chang a memory system [100, fig. 1], comprising:
a power management integrated circuit (PMIC) [110, fig. 1] operable to supply power to a dual-in-line memory module (DIMM) [as shown in figure 1, memory 102 is connected to power management controller 110 via switch 112 and feedback unit 114].
the DIMM operable to output, via a first pin, feedback information [0027, as shown in figure 1, power feedback status is provided to the PMI 110 via the bottom pin. For example, the power status feedback unit 114 obtains the memory array power status measurement by reading a voltage signal from a sense net comprising pins of the memory array 106].
and a host device [108, fig. 1] operable to:
detect the feedback information based at least in part on monitoring the first pin [0027, as shown the feedback signal is sent to the MCU 108 where it is sensed. For example, the sensed voltage level of the memory array 106 is supplied to the MCU 108 and to the PMC 110].
and apply a voltage to a second pin of the PMIC, wherein the second pin is associated with the power supplied to the DIMM [0028, 0034, fig. 1-2, as pointed out specific voltage is applied to pin of the memory 106 as shown in figure 1. For example, the Vdd array power sense net (voltage measurement pin) is performed for a particular SoC configuration by taking into account worst case delivery from the Vdd array source net ( pins) corresponding to the signal path from the array power switch 112 to the memory array 106 (see FIG. 1) and for the signal path from the memory array 106 to the power status feedback unit 114. This worst case delivery scenario takes into account current (I) times resistance (R) (I*R) drops between the two nets].
As per claim 12, Cui teaches the DIMM comprises a plurality of pins operable to couple the DIMM with the host device and the PMIC [as shown in figure 1-2 multiple arrays of Vdd’s connected to the memory and the microcontroller 108].
As per claim 13, Cui teaches the DIMM comprises a dynamic random access memory (DRAM) module [0067, other type of memory can be used].
As per claim 14, Cui teaches the feedback information conveyed via the first pin is associated with the PMIC [0027, feedback information related to specific pin of the memory].
As per claim 15, Chui teaches the feedback information conveyed via the first pin indicates a second voltage at the DIMM based at least in part on the power supplied by the PMIC [0027-0028, sense the second voltage supply to the memory].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cui (US Patent Application 20150160718) in the view of Chun (US Patent Application 20190317911).
As per claim 9, Cui does not teach manage one or more regulators of the PMIC based at least in part on the voltage applied to the second pin.
However, Chun teaches manage one or more regulators of the PMIC based at least in part on the voltage applied to the second pin [0062-0063, fig. 7 control signal from the PMIC can manage the voltage regulators].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Cui to include the method of Chun to add voltage regulator to the unit that can adjust or change the voltage level to produce a desired output.
As per claim 10, Cui does not teach disable the one or more regulators of the PMIC based at least in part on the voltage transitioning from a first level to a second level that is lower than the first level.
However, Chang teaches disable the one or more regulators of the PMIC based at least in part on the voltage transitioning from a first level to a second level that is lower than the first level [0063, the PMIC can enable corresponding voltage regulator].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Cui to include the method of Chun to add voltage regulator that can be enable and disable by the PMIC.
As per claim 11, Cui does not teach enable the one or more regulators of the PMIC based at least in part on the voltage transitioning from a first level to a second level that is higher than the first level.
However, Chun teaches enable the one or more regulators of the PMIC based at least in part on the voltage transitioning from a first level to a second level that is higher than the first level [0065, as pointed out the PMIC can disable corresponding voltage regulator].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Cui to include the method of Chun to add voltage regulator that can be enable and disable by the PMIC.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim (20190339759) teaches connectors, power supply control devices, and host interface devices including connector and power supply control device
Chun (US 20100054050) teaches apparatus and method for providing power in semiconductor memory device.
Vasudevan (US 7733075) teaches voltage sensing in a supply regulator for a suspend mode.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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