DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota (US2018/0270405A1).
As to claim 1, Ota discloses (fig. 4, fig. 12) a light detection device (100), comprising: a light detection substrate (210) having a main surface (212) and including a plurality of pixels (12) disposed in a direction along the main surface (212), (paragraphs [0042]-[0047], [0111]-[0113]); and (fig. 12) a circuit substrate (300 in which other components than the avalanche photodiode APD, are provided, i.e., peripheral circuits such as vertical scanning circuits 20, column readout circuit 30, horizontal scanning circuit 40, the control circuit 50, and the output circuit 60), (paragraphs [0041], [0111]) defines (fig. 3) a plurality of MOS switch circuits (MN1 & MP1; MN2 & MP2; MN3 & MP3) arranged in the direction along the main surface (212) and electrically (electrically) connected (connected), (paragraph [0111]) to corresponding pixels (12, pixel elements) among the plurality of pixels (12, pixel elements), wherein: each of the pixels (12, pixel elements) includes only one avalanche photodiode (APD1, APD2, APD3), (paragraphs [0055], [0060]-[0063], [0071], [0075]-[0076]) configured to operate in a (operate in a) Geiger mode (Geiger mode), (paragraphs [0052]-[0053], [0074], [0082]) while individually forming (fig. 4, fig. 12) a light receiving region (224), (paragraphs [0043]-[0046], [0112]), (fig. 12) a MOS switch circuit region (310, 322) occupied by the (fig. 3) MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3) overlaps with the avalanche photodiode (APD1, APD2, APD3) when viewed from a direction perpendicular to the main surface (212), (paragraphs [0035]-[0038], [0061]-[0063]), and (fig. 3) the avalanche photodiode (APD1, APD2, APD3) included in each of the pixels (12) is connected to one of the MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), (paragraphs [0036]-[0038], [0063], [0071]-[0072]). Ota fail to explicitly disclose an area of the MOS switch circuit region is larger than an area of an active area of the avalanche photodiode. However, as illustrated in figure 12 when viewed from a direction perpendicular to the main surface, Ota discloses an area (322) of the MOS switch circuit region (310, 322) is larger than an area (210) of an active area of the avalanche photodiode (APD1, APD2, APD3), (paragraphs [0036]-[0038], [0063], [0071]-[0072]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Ota to include an area of the MOS switch circuit region is larger than an area of an active area of the avalanche photodiode in order to easily control photoelectric change gain in a pixel and an imaging system using the imaging device resulting in setting the plurality of avalanche photodiodes to an active state or an inactive state, (see paragraphs [0006]-[0007] to Ota).
As to claim 2, Ota discloses (fig. 3) the light detection device (100) wherein the MOS switch circuits (MN1, MN2, MN3) and the avalanche photodiodes (APD1, APD2, APD3) included in the pixel (12) connected to the MOS switch circuits (MN1, MN2, MN3), (paragraphs [0035]-[0040]) are electrically (electrically) connected (connected), (paragraph [0111]) to each other through a bump electrode (242, 250, contact plugs) disposed between (fig. 12) the light detection substrate (210) and the circuit substrate (300), and the bump electrode (250, contact plugs) is disposed in the light receiving region (224) of one of the avalanche photodiodes (avalanche photodiodes, APDs) connected to the bump electrode (242, 250, contact plugs) when viewed from the direction perpendicular to the main surface (212), (paragraphs [0111]-[0113]).
As to claim 4, Ota discloses (fig. 3) the light detection device (100) wherein the MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3) include a plurality of MOS-FETs (MN1 & MP1, MN2 & MP2, MN3 & MP3) connected in parallel to each other via (N1, N2, N3) respectively, (paragraphs [0036]-[0040]).
As to claim 5, Ota discloses (fig. 12) the light detection device (100) wherein the circuit substrate (300 in which other components than the avalanche photodiode APD, are provided, i.e., peripheral circuits such as vertical scanning circuits 20, column readout circuit 30, horizontal scanning circuit 40, the control circuit 50, and the output circuit 60), (paragraphs [0041], [0111]) defines (fig. 2, fig. 3) includes a plurality of control lines (14) configured to transmit control signals (RES, SEL, GAIN) to the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), respectively, (paragraphs [0033]-[0040]), (fig. 12) each of the light detection substrate (210) and the circuit substrate (300) includes the plurality of pixels (12) and (fig. 3) the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), and includes a plurality of signal output units (INV1, INV2, INV3 & 112) configured to output signals (photoelectric conversion signals) from the pixels (12) via the MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), and the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3) included in the same signal output unit (INV1, INV2, INV3 & 112), (paragraphs [0035]-[0040]) is connected to (fig. 2) the same control line (14), (paragraphs [0033]-[0034]).
As to claim 6, Ota discloses (fig. 3) the light detection device (100) wherein the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), each included in a respective different signal output unit (INV1, INV2, INV3), (paragraphs [0035]-[0040]) is connected to (fig. 1, fig. 2) a respective different control line (14), (paragraphs [0029]-[0034]).
As to claim 7, Ota discloses (fig. 3) the light detection device (100) wherein the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), (paragraphs [0035]-[0040]) connected to (fig. 1, fig. 2) the same control line (14) is arranged in a column (column), (paragraphs [0028]-[0034]).
As to claim 8, Ota discloses (fig. 3) the light detection device (100) wherein the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3) is arranged in (fig. 1) a matrix (matrix), (paragraph [0029]) when viewed from the direction perpendicular to (fig. 12) the main surface (212), the circuit substrate (300 in which other components than the avalanche photodiode APD, are provided, i.e., peripheral circuits such as vertical scanning circuits 20, column readout circuit 30, horizontal scanning circuit 40, the control circuit 50, and the output circuit 60), (paragraphs [0041], [0111]) defines further includes (fig. 1, fig. 2) a plurality of read lines (16), (paragraph [0029]-[0033]) that electrically (electrically) connects (connects), (paragraph [0111]) a corresponding (fig. 3) MOS switch circuit (MN1 & MP1, MN2 & MP2, MN3 & MP3) among the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3) and (fig. 1) a signal processor (30) configured to process signals (signal processing), (paragraphs [0031]-[0032]) from (fig. 3) the avalanche photodiode (APD1, APD2, APD3), and the plurality of MOS switch circuits (MN1 & MP1, MN2 & MP2, MN3 & MP3), each included in a respective different signal output unit (INV1, INV2, INV3), (paragraphs [0035]-[0040]) and arranged in a column (column), is connected to (fig. 1, fig. 2) the same read line (16), (paragraphs [0029]-[0034]).
As to claim 9, Ota discloses (fig. 1) the light detection device (100) further comprising a plurality of signal processors (20, 30, 40, 60) configured to perform processing in parallel with each other in terms of time, wherein the plurality of signal processors (20, 30, 40, 60) is each connected to a respective different read line (16), (paragraphs [0029]-[0032]).
Allowable Subject Matter
Claims 3, 10-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fail to teach either singly or in combination wherein an area of the light receiving region is 5μm2 or more and 650 μm2 or less when viewed from the direction perpendicular to the main surface and wherein in the MOS switch circuits each include first, second, and third switches connected in parallel to each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DON J WILLIAMS whose telephone number is (571)272-8538. The examiner can normally be reached M-F 8 a.m.-5 p.m..
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/DON J WILLIAMS/Examiner, Art Unit 2878
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